Dear
Using BRAM (for example, RAMB16_S36_S36), I do need to implement "synchronous WRITE, asynchronous READ" FIFO.
From the following previous discussion:
I still do not get to solution.
My FIFO module has following I/O.
------------------------------ clk : in std_logic; -- common clock for "read/write" rst : in std_logic; -- reset wr_data : in std_logic_vector(32 downto 0); -- write 'data' write_in : in std_logic; -- want to 'write' read_in : in std_logic; -- want to 'read' rd_data : out std_logic_vector(32 downto 0); -- read 'data' write_out : out std_logic; -- data 'written' (or can be written) read_out : out std_logic; -- data 'read' (or can be read)
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In my implementation, always one cycle for 'write' and one cycle for 'read' occur !!
By the way, "Synchronous write, asynchronous read" was possible, when we use "look-up tables" (or slices). I wish to use BRAM to have such a behavior. It seems that some people have this experience. Please give me more hints.