Hello,
I would like to know does anyone knows, is it possible to reverse engineer an edif netlist file? I am currently developing an FPGA core. I would like to supply an evaluation version of the core, that would have all the functionality of the final core, but would operate only for a limited period of time. My fear is that there is a way to modify the evaluation version edif netlist (find and remove modules that set a time limit to the operation of the evaluation version), and thus obtain completely functional core. Can something like this be done, or am I being paranoid? Every help and clarification on this subject is most welcome.
Thanks in advance, Rastislav Struharik