Reverse engineering an EDIF file?

Hello,

I would like to know does anyone knows, is it possible to reverse engineer an edif netlist file? I am currently developing an FPGA core. I would like to supply an evaluation version of the core, that would have all the functionality of the final core, but would operate only for a limited period of time. My fear is that there is a way to modify the evaluation version edif netlist (find and remove modules that set a time limit to the operation of the evaluation version), and thus obtain completely functional core. Can something like this be done, or am I being paranoid? Every help and clarification on this subject is most welcome.

Thanks in advance, Rastislav Struharik

Reply to
Rastislav Struharik
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Sorry. An EDIF file should be pretty straight forward to reverse engineer. I have had to edit one before. You could make it difficult by obfusciating it. One method changes all names to be sequences of letters O and l and numbers

0 and 1. This would not deter those that are determined though. If there is money involved, people are determined.

You would be better off working with a good legal agreement and people who you can trust to abide by it.

Cheers, Jim

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Jim Lewis
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Reply to
Jim Lewis

I think you should distribute your design in a binary format, since it's fairly easy to reverse engineer EDIF:

Use any text editor for editing.

Use Aldec or Riviera for simulating. (Both tools handle a combined VHDL / Verilog / EDIF flow).

Use a recent version of Synplify to convert to (almost readable) schematics.

Regards, Allan.1

Reply to
Allan Herriman

Dear Allan,

Thank you for your answer. When you say binary format, what precisely do you mean? On the other hand I was thinking of using Xilinx NGC netlist instead of EDIF. Do you think this would help? I have read that NGC is a encrypted netlist format, and if there is no easy way of converting NGC to EDIF, than maybe it would be a solution to my problem.

Best regards, Rastislav

Reply to
rasti123

You can convert the edif file into Verilog of VHDL by running the Xilinx programs edif2ngd followed by an ngd2ver or ngd2vhdl. What you get is gate level so it's not easy to work with but it's at least minimally human readable.

Reply to
B. Joshua Rosen

NGC would be better than EDIF.

You will probably also have to ship something that will allow your customers to simulate the core. This is typically done by shipping a pre-compiled library (to suit whatever simulator your customers use) with an NDA (non-disclosure agreement).

Regards, Allan.

Reply to
Allan Herriman

One of my assignments 10 years ago was to develop a routing engine for Lattice Semi's ISP PLD's. It invoved parsing and EDIF file into logic equations. Jim is right, it would be easy to reverse engineer.

The best advice I ever got about legal agreements was this: "Get to know who you're dealing with. There is no document that can make it worthwhile to deal with someone who is dishonorable."

If you can protect the design by making it difficult and expensive to reverse engineer ... that may be time and money well spent. It also gives you and your clients a better competitive advantage.

Frank Raffaeli

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Reply to
Frank Raffaeli

Hi,

I think you have got enough ideas for this issue.

I want to learn, how can i set time limit for a core. As you said, how can i make my .edf to work fine for limited period of time?

Can you help me on this?

Regards, Muthu

Reply to
Muthu

In comp.lang.vhdl Jim Lewis wrote: : You would be better off working with a good legal agreement : and people who you can trust to abide by it.

One does not really make an agreement over a deadline. It is just sometimes easier to uncompile things, providing this is possible. (If you are talking only about bying a licence, this should be quick providing you can arrange the money quickly.)

I have been working over a project that the technical person claims that the bug does not exists or it was fixed a long time ago, (do not remember anymore which one ) despite we had showed wery clearly that the big is there. (In reality the bug has been fixed on a subsequent, but incompatible release of the program, which was not compatible with out software at that time.)

We send the uncompiled file to that person, with exlanation what happens, when why. ... The fix got into the next sevice release.

We were not major client, they would most likely been more likely to lose us, that to give out sourcecode to debug a bug "which is not there".

Reply to
Joonas Timo Taavetti Kekoni

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