Synchronizing multibit bus

Since the indivdual bits of the multi bit bus may change at their own time, sampling at odd intervals may result in sampled bus pattern that are just temporary in nature. Thus the sampled pattern may be wrong. Only the gray code is save to sample at odd intervals as only one-bit changes are allowed.

Apart from that, the multi bit bus could also contain its own clock, showing when the data is valid.

Rene

There seems to be a misconception that you can Gray-code any bus. Not true. Gray-coding applies only to counters, where it guarantees that only one bit changes on any transition. There is no "general purpose" Gray coding ... Peter Alfke, Xilinx Applications

Sure, a bus cannot live from 1 bit transitions. I was unclear about that. A clock as qualifier is appropriate.

Rene

I'm not sure why you would want to, but a bus with single bit transitions could work. It would be very ineffiecient. You would need n wires to send n states. Suppose you wanted to send a four bit command to some remote device on a different clock, and you could not send a clock with the data (I can't think of realistic reasons why, but humor me).

So on each clock, the sending circuit would decode the four bit command to one of sixteen bits to XOR with the current state of the bus. This would toggle one bit of the sixteen bus wires to indicate which command was being sent. The receiving circuit would look for one bit to change and would decode this to the correct command.

I can't think of any practical examples, but maybe there is one somewhere.

-- Phil Hays Phil-hays at posting domain (- .net + .com) should work for email

synchroniz

Yes, this is called the correlation issue. You can put any number o

flip-flop synchronizers in the design, but you need differen synchronizers for each individual bit (remember, flip flops are b design for single bits, not busses). Thus each bit's metastabilit is independent of each other

So, you can have one of the bits in the bus go metastable, and eve

though there are multiple synchronizers to protect you from readin the metastable bit, its metastability delayed the bit propagation b one or more clock cycles. Thus, the end result is that all the bit look correct except one (because that bit is one or more clock cycle delayed)