EDK : PPC405 Interrupt question

No. This was the first thing I got to work! I had my own hardware generate an interrupt signal and I used the Xilinx BSP for the Power PC to hook the interrupts in software.

I have noticed though that the interrupt latency is quite high on the Power PC (10uS! @ 100Mhz clock). Not sure where the weak link was in the software chain. I was using the Xilinx provide functions for hooking my own interrupt function. I had a project tha continuously held the critical interrupt high. In the ISR, I toggled the LED. At a

-Eli

That means each ISR took ~1000 wallclock cycles. Were you executing out of internal BRAM or external DRAM? Were the caches enabled?

Paul

Everything was out of BRAM. Can't remember if caches were enable. I have to check the project (Was about 6 months ago).

The only thing else I could figure was that my bit I was toggling was a GPIO on the OPB. I know that OPB is very slow and may be hanging things up. Either that or the Xilinx BSP interrupt functions are very bloated.

Never got that figured out. My resolution was to make my own DMA controller on the PLB to transfer data over the bus. I never hooked anything system critical to an interrupt, I always used hardware. Only things like the serial port, etc. were tied to an interrupt.

-Eli

You don't need an extra interrupt controller if you connect two devices as you described. However, two interrupts will have different priority, and the critical interrupt (interrupt from critical interrupt port) will interrupt the external interrupt (interrupt from external interrupt port), and so if you don't write your interrupt handler code carefully, you may face some weird behaviors.

Sewook Wee