I have an Atmel AT94K40 FPGA and I need to synthesize (by writing VHDL) a dual clock FIFO (a FIFO with different read and write clock). The problem is that the Atmel macro-generator has the ability to generate only single clock FIFO. Is it possible that Atmel did not think to include the possibility of creating dual clock FIFO's in an efficient way??? Have I to design a FIFO by myself with "glue logic"?? In this way I could not use the "FreeRAM" feature of the FPGA, and the resource use would be critical. Just to simulate my design, now I'm using a dual clock FIFO created with the Altera macro generator, which uses a LPM_FIFO block. Do you think I could try to synthesize this LPM_FIFO block in Atmel FPGA?
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