What is the cheapest line of volatile Xilinx´s FPGAs? What is the relation between Altera´s LEs and Xilinx´s Slices? I need the cheapest Xilinx FPGA (or from any other manufacturer) that has the aproximated same capacity as a 700-1000 Altera´s LEs. What would you suggest?
If you won't be in production until next year, the cheapest solution will likely be the Spartan 3. If you need parts now, it would likely be the Spartan IIE. Both families have about 1500 logic cells in the smallest part, regardless of what the data sheets says. Xilinx likes to pad the number since they feel they have "uber-cells" which count as more than 1 each. But then again, they don't define the term "logic cell", so I guess they can count them any way they want.
Rick "rickman" Collins
Not really, the "padding" is exactly 12.5%, so it has been defined and is deterministic. Marketing wants to get credit for the additional multiplexers that the competition does not have. If you are a purist, just count slices and devide by 2, or multiply CLBs by 4 (Virtex and Spartan2) or by 8 (Virtex2 and Spartan3). That gets you the number of LUTs+flip-flops.
The XC2S50E-6PQ208C is in-stock at Digi-Key for $14.55 quantity 1. The cheapest theoretical price I have seen for the XC3S50J is $23.85 (for a -4TQ144CES), and I have yet to see a distributor claim stock.
Personally, I find marketing to frequently be irritating and annoying. When I try to get technical information from a data sheet or web site and marketing distorts or glamorizes the information so much that it interferes with my work, I find that both an insult to my intelligence and a waste of my time.
I am aware of why Xilinx marketing distorts the cell counts and I don't really care by how much. I care about the fact that I have to ignore a column of data in a data sheet as marketing hype and use a calculator to get the *real* numbers. Clearly the marketing people don't think we can add and multiply ourselves.
Rick "rickman" Collins
Rick, I will not defend the +12,5%, but I can explain it:
It is the price we all pay for the intense and sometimes ruthless competition in this market. Without a bloodthirsty competitor "in our rear-view mirror", we would be gentlemanlike and give you conservative numbers. But the way it is, our marketing folks think it would throw away some really (really!) powerful features if they are not somehow represented in the numbers. Each Xilinx Logic Cell does more than an Altera LE, there can be no doubt about that.
This is not an excuse (personally I agree with you), but an explanation.
Peter Alfke ==========================
rickman wrote: I care about the fact that I have to ignore a
I might as well give the Altera view -- 12.5% is a gross overstatement of the relative abilities of a Virtex LC vs. a Stratix LE. Our data suggests that nearly the reverse is true (about a 9% advantage for Stratix). Please see the following whitepaper for our reasoning and data. As you can see from Figure 1, your mileage will vary -- depending on your design, you could see vast density advantages from one architecture or the other.
If we wanted to, we could start counting our M512 blocks as logic, as they can be used for shift-registers, small memories, and soft multipliers, but we don't bother.
Bottom line -- you really need to compile *your* design to both Stratix and Virtex (or whatever families you are interested in) before you will really know what the story is density. Averages don't matter much to you if yours is that design that gets hosed in one architecture or the other!
Is just recompiling good enough to be interesting? (Yes, better than nothing and I'll take whatever I can get.)
Suppose I start with some "clean" vendor neutral code. How much do I gain in speed or space by hacking the code to take advantage of special features of an architecture?
If I have code that has been tweaked for one vendor, does that get in the way (as compared to not help) if I just compile it for another architecture?
How often is real code thoroughly tied to a particular chip? Say by adjusting the pipeline to fit well. Or using a multiplier as a shifter because it would otherwise be idle. Or do all interesting FPGAs these days have multipliers and dual port RAMs and ... that are reasonably equivalent?
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The equation for utilization is very complex. For arithmetic data path however, I do find that the Xilinx structure permits a higher density measured in LUTs occupied when comparing designs for the same algorithm but optimized for the particular device. This is due partially to the fact that the Altera carry chain breaks the LUTs into a pair of 3 LUTs so your arithmetic is
2 input arithmetic where Xilinx's is 4 input arithmetic. Granted, Altera has greatly improved the situation by adding dedicated gating for doing an adder-subtracter in one level, as well as logic to permit an accumulator with load, which are probably the most common use of more than two input arithmetic. To be fair, the average user is not going to fully use the Xilinx capability because the synthesis tools do not do a great job at inferring more complex structures such as an add/mux or mux/add etc. In order to use that, you more or less need to do some very careful coding. Same is true for taking advantage of the SRL16s.
The fact of the matter is, I think both vendor's numbers are slanted. Unless you do the design with the specific architecture in mind, you are not going to get optimum utilization of that array. A design that is optimized for one array is going to generally be a poor fit for another. Presumably, both vendors have taken a design or designs that were targetted to their parts, and then ported those designs to the competition to come up with these numbers. In both cases, naturally, their device is going to show superior results simply because the design database they are drawing upon was optimized to their parts.
As I've stated many times before, the comparis> I might as well give the Altera view -- 12.5% is a gross overstatement of
--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.
No problem at all. 2 LUTs with F5 enabled may by double the vertical size of an data path bit. But as one is not using the carry chain when using F5 (the Lut/Fn/carry MUX ensures this) it is no problem to "zigzag" data path bits. Put each pair of data path bits into 2 vertical stripes of slices, very simple:
And with F5 being "vertical" it can be used (combining 2 LUTS to an 8 input AND or OR) in the corresponding control logic of an 1 slice wide data path segment, without having to sacrifice an 2nd slice or use up logic of the next (or even worse previous) segments control logic space.
Now F6 using 2 horizontally neighboring slices (which is what you suggest for F5), that messes this scheme up.
Or the 12.5% stand for "LUT-saving and next to no delay" 2nd level in multiplexers (halves levels, 2/3s LUT usage), usefull RAM (inclusive F5-using 32bit, same trick!) and "I don't reconfigure LUTs" useless SRL16s. :-)
Everyone sees their 1/8th of an LUT in different extra features.
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- hardware runs the world, software controls the hardware code generates the software, have you coded today?
You failed to take into account the many IP cores that are available that are optimized for a particular architecture.
Examine the vendor's own free IP, for fee IP, and the community around that vendor for the number of independent or partner vendors of IP.
You don't always have to suddenly create the most complex and highest performing logic out of thin air (as that is a tough job for the best of us).
And don't forget the many talented consultants that create product specific IP that beats the performance of the best cores that folks may offer.
But it is true that the more specialized and targeted you get, the less likely it will port conveniently to any other device, other than the manufacturer that it was originally on (and not even then if it is a new architecture).
Aust> The equation for utilization is very complex. For arithmetic data path
My point is that as an engineer, I can figure out what is best for my design. If I can't, then shame on me. But giving me phoney numbers (which is what the Xilinx cell counts are no matter how marketing justifies them) just makes the vendor look bad to engineers. If Xilinx has better cells, then tell me that! Don't try to tell me you have more cells than you really do, that is utter nonsense!!!
I have always and expect *will* always resent the "spin" that marketing puts on what is really a very technical business. I remember the first time I noticed an overly "marketized" web site that was hard to view because of the large graphic files that added nothing to the information I wanted. I also remember the first time an information file was altered by marketing so much that it was not usable on any of the machines I had available. I have yet to see any added value in any of the documentation or even in the advertising that the marketing people put out. Heck, it was only a few weeks ago that I even learned what a "platform" chip was after having read about it in FPGA advertising for what... three or four years?
Before we let Shakespeare kill all the lawyers, let's kill all the marketeers!
Paul Leventis wrote:
Rick "rickman" Collins