LUT in fpga

Hi all,

I am new to FPGA architecture. To know the what does LUT means I came across few good articles posted in this group. But still not completely clear about it.

A 4-bit input LUT in spartan 2 can be implemented as Function Generator or as 16-bit ROM ... accepted . But I cant imagine it as a 16-bit RAM or a shift Register. If it is a

16-bit Ram / Shift Register then where is the input port. I think input port to LUT is only available during configuration of FPGA but not to the designer.

Also please suggest me some good books to know the architecture of FPGA.

Thanks .

-- Mohammed A Khader.

Reply to
Mohammed A Khader
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That's the trick ;) A 'pure' LUT can't be shift register or RAM, but if you allow to interconnect the configuration logic with user logic, you can reconfigure the LUT content at run time (write port) and use the 'normal' LUT input as read port.

For the shift register, I'm not sure but I think each 16 bits of memory inside a LUT is like a register, so when in a special mode, each input is connected to the output of the previous one, so you have a shift register and the "normal" LUT access allows you to "tap" somewhere in the chain.

So yes a pure LUT can't be thos things, but the way theses reconfigurable LUTs are implemented in FPGA have tweaks so the can act as RAM/SRL ...


Reply to
Sylvain Munaut


Sorry but a LUT is : Logic Unit Table -> a LUT can only do combinatory works (AND OR XOR ...). CLB is: Configurated Logic Block -> a CLB include one LUT followed by one Flip-Flop in minimum.

For some Xilinx FPGA the CLB can be use as RAM or as SRL (not the LUT itself ;-) )

After that advice, please open a FPGA datasheet for understanding it specific architecture !

LUT - CLB - CLB interconnection - IOB ...

regards, Laurent

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Reply to
Laurent Gauch

Let me correct this: A LUT is basically a 16-bit ROM, but Xilinx has added a few things inside the LUT.

  1. Since the LUT content must be written by configuration, the ROM is really writable, and Xilinx then allows the user logic to also write data into it. That's the distributed RAM or LUT-RAM.
  2. Since the LUT can be used as a RAM, it is not too difficult to convert it into a shift register, the SRL16, which uses a clever trick to act as intermediry storage between the shiftregister bits.

All of this happens inside the Xilinx LUT (competitors do not have these extra features) The CLB then adds flip-flops, multiplexers, carry logic and interconnects.

But I do agree with Laurent: Read the data sheet and the user manual. That's why we wrote them... Peter Alfke, Xilinx Applications

Reply to
Peter Alfke

Hey Laurent, Is that the Academy Français's version? In English speaking countries LUT means Look Up Table! ;-) Cheers, Syms.

Reply to


You need to accept it more fully :-) Think of a ROM the following way:

16 flipflops (storage) each one either set or clear, and no clock to the flipflops. Take the output of the 16 FFs, and connect them to a 16 to 1 mux. The mux will need 4 control lines. When the control lines are 0000, the output of the mux is the value in FF_0 , when it is 1111, the mux output is the value in FF_15.

So really, there is no difference between calling it a LUT or a ROM. It holds 16 bits, and via the mux, you can select to look at any 1 bit.

Let me help your imagination, in stages.

First, lets take the 16 FFs I described above (without clocks, but somehow preset to either 0 or 1), and lets add an async set and clear line to each FF. We can now force the value of each FF via these new signals. This is equivalent (but not actually) the way the FPGA uses the configuration data to initialize the FFs that make up the ROM/LUT.

Now, lets add a common D and common clock input to each FF, and also a clock enable to each FF (16 of them). Add a 4 line to 16 line decoder and connect it to the 16 clock enable lines. The 4 inputs to the decoder are connected to the 4 control lines of the output selection mux. So when these 4 lines are 0000, the output mux shows us the content of FF_0, and if we put a 0 or 1 on the D input line (that goes to all FFs), and apply a rising clock edge (that goes to all FFs), then only FF_0 will be loaded with the data on D, because the decoder is only enabling the clock on FF_0. What we now have is a RAM.

There are 3 extra inputs, Clock, Write Enable (WE), and Data (D)

To turn the 16 FFs into a shiftregister, we need to add some additional logic so that rather than only clocking 1 FF at a time (RAM mode), we enable clocking of all 16 FFs, and rather that the 16 D inputs all comming from a common D signal, the D signal only connects to FF_0. The D of FF_n connects to the output of the prior FF, Q_n-1. Thus we have a shiftregister.

This is true of the early Xilinx FPGA products, the XC2000 and XC3000 families. All Xilinx FPGA products since the XC4000 family (1990) have had the RAM capability, and the SRL capability became available in the Virtex-II product line (2001).

The US patent office makes available all patents on-line, for free.

You "just" need to search for the appropriate patent.

start here:

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Try search terms like "RAM" and "XILINX". Here let me help you. try 5566123 , it includes complete detailed schematics, including something you didn't ask about, Dual-Port.

Unfortunately the foll>DO NOT CONFUSE LUT and CLB

Mohammed never mentioned CLBs


No. It is Look Up Table.

True enough, but irrelevant to the question.

No. The LUT IS what is used to implement the RAM or SRL.


Happy learning, Philip

=================== Philip Freidin Host for

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Reply to
Philip Freidin

Hi everyone,

And so am I: yet another hobbyist starting out with the Spartan-3 board

- and having a great time so far.

Reply to
Paul Boven

If you want to use a LUT as a 16b table with values you fill in driven by 4b inputs, forget the old schematic way. Learn either V language synthesis subset, also get the Doug Smith and Palnitker books too.

in pseudo Verilog/HDL/C

wire6 my7b; wire4 my4binput;

switch(my4binput) { case 0: my7b=1; // the actual segment values are in the starter kit manual. case 1: my7b=0; case 2: my7b=1; case 3: my7b=1; ... case 15: my7b=42; }

Should synthesize perfectly well and simulate after you fix up the syntax.

Also in the webpack find your way over to templates menu for examples of most everything (simple) you could cut n paste n edit. Case statements are in there.


johnjakson at usa dot com

Reply to

Found it: In component properties, set the INIT attribute. I had tried this before but hadn't yet realised that this value needs to be in hexadecimal, binary won't fit.

Regards, Paul Boven.

Reply to
Paul Boven

If your question means "where can I set the INIT values", you can do this in your source code either as a generic on the LUT or an attribute on the LUT.

If you meant "how can I check the INIT value assigned", this can be done with FPGA Editor (not available with Webpack), which will show you the logic equation associated with each LUT.

Reply to
Jim George

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