MAP failes after inserting ILA and ICON cores to the design

I forgot to mention it's a Xilinx Virtex2-Pro device ...

Ran

form required.

i_ila/ila/i_no_d/u_ila/u_trig/u_tm/g_nmu/1/u_m/u_mu/i_mut_gand/u_match/pd_rpm/i_

will not

[...]

error.

[...]

Howdy Ran,

Three things come to mind when looking over this log:

1. Is the device over-full? When you run with -timing, what is the LUT and FF utilization?

1. Is the RPM for the ILA/ICON core too tall for the device you are targetting? Any idea how tall your core is? You mentioned you were targetting a V2Pro, but which one?

2. I don't recall - for the ILA/ICON core, are you forced to use RPM's? I'm thinking you are, but if not, maybe try without? Good luck,

Marc

Thanks Marc for your answer.

1. I don't think my device is over-full. Here is a device utilization summary of a successful MAP run (without the ChipScope cores and with the "-timing" option):

**************************************************** START HERE

**************************************************** Release 6.3.02i Map G.31a Xilinx Mapping Report File for Design 'pcix_3port_bridge'

Design Information

------------------ Command Line : /usr/local/apps/xilinx62i/bin/lin/map -intstyle ise -p xc2vp30-ff896-6 -ol high -timing -cm area -pr b -k 4 -c 100 -tx off -o gtw_map.ncd gtw.ngd gtw.pcf Target Device : x2vp30 Target Package : ff896 Target Speed : -6 Mapper Version : virtex2p -- $Revision: 1.16.8.2 $ Mapped Date : Fri Dec 17 01:14:19 2004

Design Summary

-------------- Number of errors: 0 Number of warnings: 1213 Logic Utilization: Total Number Slice Registers: 17,111 out of 27,392 62% Number used as Flip Flops: 17,107 Number used as Latches: 4 Number of 4 input LUTs: 20,728 out of 27,392 75% Logic Distribution: Number of occupied Slices: 13,655 out of 13,696 99% Total Number 4 input LUTs: 24,290 out of 27,392 88% Number used as logic: 20,728 Number used as a route-thru: 1,332 Number used for Dual Port RAMs: 2,140 (Two LUTs used per Dual Port RAM) Number used as Shift registers: 90

Number of bonded IOBs: 416 out of 556 74% IOB Flip Flops: 1,035 IOB Dual-Data Rate Flops: 17 Number of PPC405s: 0 out of 2 0% Number of Block RAMs: 66 out of 136 48% Number of GCLKs: 8 out of 16 50% Number of DCMs: 6 out of 8 75% Number of GTs: 0 out of 8 0% Number of GT10s: 0 out of 0 0%

Total equivalent gate count for design: 4,941,440 Additional JTAG gate count for IOBs: 19,968 Peak Memory Usage: 521 MB

**************************************************** END HERE ****************************************************

2+3. I am using V2Pro-30 (package ff896, speed grade -6). I don't know "how tall" is my device. What does that mean ? I tried unchecking the "use RPM" checkbox of the ChipScope ILA generator, but results were the same. ICON core doesn't have a "use RPM" checkbox.

I did another run, this time with ISE 6.3 SP3, and got a different MAP results (still failes):

**************************************************** START HERE **************************************************** Release 6.3.03i Map G.38 Xilinx Mapping Report File for Design 'pcix_3port_bridge'

Design Information

------------------ Command Line : /usr/local/apps/xilinx63i/bin/lin/map -intstyle ise -p xc2vp30-ff896-6 -ol high -timing -cm area -pr b -k 4 -c 100 -tx off -o gtw_map.ncd gtw.ngd gtw.pcf Target Device : x2vp30 Target Package : ff896 Target Speed : -6 Mapper Version : virtex2p -- $Revision: 1.16.8.2 $ Mapped Date : Thu Dec 23 17:18:07 2004

Design Summary

-------------- Number of errors : 123 Number of warnings : 4

Section 1 - Errors

------------------ ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT i_ila_rpm/i_no_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/cfg_data_4 (0, 0) FF i_ila_rpm/i_no_d/u_ila/u_g2_sq/u_capctrl/u_cap_addrgen/cfg_data_4 (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT app_port/NFS_engine/nfs_stream_manager/checksum_s6[0] (0,

0) FF app_port/NFS_engine/nfs_stream_manager/checksum_s6[0] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT

sdram_port/sdram_dest/sdram_ddr_lb/ddr_datapath[8].ddr_datapath/reset_strobe (0, 0) FF

sdram_port/sdram_dest/sdram_ddr_lb/ddr_datapath[8].ddr_datapath/reset_strobe (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT app_reset_module/reset_out_i_n (0, 0) FF app_reset_module/reset_out_i_n (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sdram_reset_module/reset_out_i_n (0, 0) FF sdram_reset_module/reset_out_i_n (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT app_port/NFS_engine/last_illegal_command[6] (0, 0) FF app_port/NFS_engine/last_illegal_command[6] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT

sdram_port/sdram_dest/sdram_ddr_lb/ddr_datapath[6].ddr_datapath/reset_strobe (0, 0) FF

sdram_port/sdram_dest/sdram_ddr_lb/ddr_datapath[6].ddr_datapath/reset_strobe (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT

sdram_port/sdram_dest/sdram_ddr_lb/ddr_datapath[3].ddr_datapath/reset_strobe (0, 0) FF

sdram_port/sdram_dest/sdram_ddr_lb/ddr_datapath[3].ddr_datapath/reset_strobe (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT app_port/NFS_engine/nfs_stream_manager/conn_index_in_pipe2[11] (0,

0) FF app_port/NFS_engine/nfs_stream_manager/conn_index_in_pipe2[11] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT

sdram_port/sdram_dest/sdram_ddr_lb/ddr_datapath[1].ddr_datapath/reset_strobe (0, 0) FF

sdram_port/sdram_dest/sdram_ddr_lb/ddr_datapath[1].ddr_datapath/reset_strobe (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT app_port/NFS_engine/host_cst_wr_data[84] (0, 0) FF app_port/NFS_engine/host_cst_wr_data[84] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT

sdram_port/sdram_dest/sdram_ddr_lb/ddr_datapath[1].ddr_datapath/d_req1_neg1x (0, 0) FF

sdram_port/sdram_dest/sdram_ddr_lb/ddr_datapath[1].ddr_datapath/d_req1_neg1x (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT app_port/NFS_engine/stop_status[0] (0, 0) FF app_port/NFS_engine/stop_status[0] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT app_port/NFS_engine/last_illegal_command_index[10] (0, 0) FF app_port/NFS_engine/last_illegal_command_index[10] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sdram_port/sdram_dest/sdram_ddr_lb/ras_1_0_tmp_d_array_0[0] (0, 0) FF sdram_port/sdram_dest/sdram_ddr_lb/ras_1_0_tmp_d_array_0[0] (0,

1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT packet_fifo_toe_to_gw_nfs/command_fifo/rd_addr[4] (0, 0) FF packet_fifo_toe_to_gw_nfs/command_fifo/rd_addr[4] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sdram_port/sdram_dest/sdram_ddr_lb/ecc_dataout[125] (0, 0) FF sdram_port/sdram_dest/sdram_ddr_lb/ecc_dataout[125] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sdram_port/sdram_dest/sdram_ddr_lb/dm_in_d[9] (0, 0) FF sdram_port/sdram_dest/sdram_ddr_lb/dm_in_d[9] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT

sdram_port/sdram_dest/sdram_ddr_lb/ddr_datapath[4].ddr_datapath/reset_strobe (0, 0) FF

sdram_port/sdram_dest/sdram_ddr_lb/ddr_datapath[4].ddr_datapath/reset_strobe (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT app_port/NFS_engine/nfs_stream_manager/conn_wptr_s6[0] (0,

0) FF app_port/NFS_engine/nfs_stream_manager/conn_wptr_s6[0] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT app_port/NFS_engine/last_illegal_length_index[10] (0, 0) FF app_port/NFS_engine/last_illegal_length_index[10] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT host_port/primary_pcix_if/pcix_if/pcix_targ_if/pcix_xfer (0, 0) FF host_port/primary_pcix_if/pcix_if/pcix_targ_if/pcix_xfer (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT nfssp_to_gw_sdram_pkt_wr_data[122] (0, 0) FF nfssp_to_gw_sdram_pkt_wr_data[122] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sdram_port/sdram_dest/sdram_ddr_lb/sa_1_tmp_d_array_0[0] (0, 0) FF sdram_port/sdram_dest/sdram_ddr_lb/sa_1_tmp_d_array_0[0] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT app_port/NFS_engine/nfs_stream_manager/conn_wptr_s6[2] (0,

0) FF app_port/NFS_engine/nfs_stream_manager/conn_wptr_s6[2] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sdram_port/sdram_dest/sdram_ddr_lb/sa_1_tmp_d_array_0[13] (0, 0) FF sdram_port/sdram_dest/sdram_ddr_lb/sa_1_tmp_d_array_0[13] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT app_port/NFS_engine/nfs_stream_manager/conn_wptr_s6[3] (0,

0) FF app_port/NFS_engine/nfs_stream_manager/conn_wptr_s6[3] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sdram_port/sdram_dest/sdram_ddr_lb/we_0_tmp_d_array_0[0] (0, 0) FF sdram_port/sdram_dest/sdram_ddr_lb/we_0_tmp_d_array_0[0] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sdram_port/sdram_dest/sdram_ddr_lb/sa_1_tmp_d_array_0[2] (0, 0) FF sdram_port/sdram_dest/sdram_ddr_lb/sa_1_tmp_d_array_0[2] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT toe_port/toe_secondary_pcix_if/pcix_if/pcix_datapath/r_repeat_d0 (0,

0) FF toe_port/toe_secondary_pcix_if/pcix_if/pcix_datapath/r_repeat_d0 (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT i_ila_rpm/i_no_d/u_ila/icap_ext_trigout (0, 0) FF i_ila_rpm/i_no_d/u_ila/icap_ext_trigout (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT app_port/NFS_engine/nfs_stream_manager/write_be_s8[3] (0,

0) FF app_port/NFS_engine/nfs_stream_manager/write_be_s8[3] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT app_port/NFS_engine/wbp_fifo_empty_flag (0, 0) FF app_port/NFS_engine/wbp_fifo_empty_flag (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT i_ila_rpm/i_no_d/u_ila/itrigger (0, 0) FF i_ila_rpm/i_no_d/u_ila/itrigger (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sdram_port/sdram_dest/sdram_ddr_lb/fastinit/fastsdram/wc_zero (0, 0) FF sdram_port/sdram_dest/sdram_ddr_lb/fastinit/fastsdram/wc_zero (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT app_port/NFS_engine/nfs_stream_manager/conn_length_s6[1] (0, 0) FF app_port/NFS_engine/nfs_stream_manager/conn_length_s6[1] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sdram_port/sdram_dest/sdram_ddr_lb/sa_1_tmp_d_array_0[11] (0, 0) FF sdram_port/sdram_dest/sdram_ddr_lb/sa_1_tmp_d_array_0[11] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT host_port/primary_pcix_if/pcix_if/pcix_targ_if/shadow_pci_ack64_n_o (0, 0) FF host_port/primary_pcix_if/pcix_if/pcix_targ_if/shadow_pci_ack64_n_o (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT

host_port/primary_pcix_if/cfg_bridge2_dev1/bridge1_cfg_regs/primary_pci_recei ved_target_abort (0, 0) FF

host_port/primary_pcix_if/cfg_bridge2_dev1/bridge1_cfg_regs/primary_pci_recei ved_target_abort (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT host_port/primary_pcix_if/pcix_if/pcix_init_if/local_rd (0,

0) FF host_port/primary_pcix_if/pcix_if/pcix_init_if/local_rd (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT packet_fifo_gw_sdram_to_fc/command_fifo/wr_addr[2] (0, 0) FF packet_fifo_gw_sdram_to_fc/command_fifo/wr_addr[2] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT packet_fifo_host_to_toe/data_fifo/fifo_ram/r_wr_en (0, 0) FF packet_fifo_host_to_toe/data_fifo/fifo_ram/r_wr_en (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT

host_port/primary_pcix_if/cfg_bridge2_dev1/bridge0_cfg_regs/primary_pci_maste r_data_parity_error (0, 0) FF

host_port/primary_pcix_if/cfg_bridge2_dev1/bridge0_cfg_regs/primary_pci_maste r_data_parity_error (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT packet_fifo_host_to_fc/data_fifo/fifo_ram/r_wr_en (0, 0) FF packet_fifo_host_to_fc/data_fifo/fifo_ram/r_wr_en (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT

sdram_port/sdram_dest/sdram_ddr_lb/ddr_datapath[7].ddr_datapath/reset_strobe (0, 0) FF

sdram_port/sdram_dest/sdram_ddr_lb/ddr_datapath[7].ddr_datapath/reset_strobe (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT app_port/NFS_engine/nfs_stream_manager/wbp_ptr_s6[0] (0, 0) FF app_port/NFS_engine/nfs_stream_manager/wbp_ptr_s6[0] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sdram_port/sdram_dest/sdram_ddr_lb/sa_i[12] (0, 0) FF sdram_port/sdram_dest/sdram_ddr_lb/sa_i[12] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sdram_port/sdram_dest/sdram_ddr_lb/cs_tmp_d_array_0[0] (0,

0) FF sdram_port/sdram_dest/sdram_ddr_lb/cs_tmp_d_array_0[0] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sdram_port/sdram_dest/sdram_ddr_lb/sa_1_tmp_d_array_0[4] (0, 0) FF sdram_port/sdram_dest/sdram_ddr_lb/sa_1_tmp_d_array_0[4] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT app_port/NFS_engine/nfs_stream_manager/wbp_ptr_s6[1] (0, 0) FF app_port/NFS_engine/nfs_stream_manager/wbp_ptr_s6[1] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sdram_port/sdram_dest/sdram_ddr_lb/dm_in_d[16] (0, 0) FF sdram_port/sdram_dest/sdram_ddr_lb/dm_in_d[16] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT toe_to_gw_nfs_pkt_rd_ack (0, 0) FF toe_to_gw_nfs_pkt_rd_ack (0,

1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT

host_port/primary_pcix_if/cfg_bridge2_dev1/bridge0_decode/host_targ_cs[3] (0,

0) FF

host_port/primary_pcix_if/cfg_bridge2_dev1/bridge0_decode/host_targ_cs[3] (0,

1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT gw_sdram_to_nfssp_pkt_rd_ack (0, 0) FF gw_sdram_to_nfssp_pkt_rd_ack (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT

sdram_port/sdram_dest/sdram_ddr_lb/ddr_datapath[2].ddr_datapath/reset_strobe (0, 0) FF

sdram_port/sdram_dest/sdram_ddr_lb/ddr_datapath[2].ddr_datapath/reset_strobe (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sdram_port/sdram_dest/sdram_ddr_lb/sa_1_tmp_d_array_0[9] (0, 0) FF sdram_port/sdram_dest/sdram_ddr_lb/sa_1_tmp_d_array_0[9] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT i_ila_rpm/i_no_d/u_ila/idata_0 (0, 0) FF i_ila_rpm/i_no_d/u_ila/idata_0 (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT i_ila_rpm/i_no_d/u_ila/idata_1 (0, 0) FF i_ila_rpm/i_no_d/u_ila/idata_1 (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT i_ila_rpm/i_no_d/u_ila/idata_2 (0, 0) FF i_ila_rpm/i_no_d/u_ila/idata_2 (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT i_ila_rpm/i_no_d/u_ila/idata_3 (0, 0) FF i_ila_rpm/i_no_d/u_ila/idata_3 (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT i_ila_rpm/i_no_d/u_ila/idata_4 (0, 0) FF i_ila_rpm/i_no_d/u_ila/idata_4 (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT i_ila_rpm/i_no_d/u_ila/idata_5 (0, 0) FF i_ila_rpm/i_no_d/u_ila/idata_5 (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT i_ila_rpm/i_no_d/u_ila/idata_6 (0, 0) FF i_ila_rpm/i_no_d/u_ila/idata_6 (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT i_ila_rpm/i_no_d/u_ila/idata_7 (0, 0) FF i_ila_rpm/i_no_d/u_ila/idata_7 (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT i_ila_rpm/i_no_d/u_ila/idata_8 (0, 0) FF i_ila_rpm/i_no_d/u_ila/idata_8 (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT i_ila_rpm/i_no_d/u_ila/idata_9 (0, 0) FF i_ila_rpm/i_no_d/u_ila/idata_9 (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT i_ila_rpm/i_no_d/u_ila/idata_10 (0, 0) FF i_ila_rpm/i_no_d/u_ila/idata_10 (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT i_ila_rpm/i_no_d/u_ila/idata_11 (0, 0) FF i_ila_rpm/i_no_d/u_ila/idata_11 (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT i_ila_rpm/i_no_d/u_ila/idata_12 (0, 0) FF i_ila_rpm/i_no_d/u_ila/idata_12 (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT i_ila_rpm/i_no_d/u_ila/idata_13 (0, 0) FF i_ila_rpm/i_no_d/u_ila/idata_13 (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT i_ila_rpm/i_no_d/u_ila/idata_14 (0, 0) FF i_ila_rpm/i_no_d/u_ila/idata_14 (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT i_ila_rpm/i_no_d/u_ila/idata_15 (0, 0) FF i_ila_rpm/i_no_d/u_ila/idata_15 (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT i_ila_rpm/i_no_d/u_ila/idata_16 (0, 0) FF i_ila_rpm/i_no_d/u_ila/idata_16 (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT i_ila_rpm/i_no_d/u_ila/idata_17 (0, 0) FF i_ila_rpm/i_no_d/u_ila/idata_17 (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT i_ila_rpm/i_no_d/u_ila/idata_18 (0, 0) FF i_ila_rpm/i_no_d/u_ila/idata_18 (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT i_ila_rpm/i_no_d/u_ila/idata_19 (0, 0) FF i_ila_rpm/i_no_d/u_ila/idata_19 (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sdram_port/sdram_dest/sdram_ddr_lb/sa_1_tmp_d_array_0[6] (0, 0) FF sdram_port/sdram_dest/sdram_ddr_lb/sa_1_tmp_d_array_0[6] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT toe_port/toe_secondary_pcix_if/pcix_if/init_wr_data_phase (0, 0) FF toe_port/toe_secondary_pcix_if/pcix_if/init_wr_data_phase (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT app_port/NFS_engine/nfs_stream_manager/wbp_ptr_s6[12] (0,

0) FF app_port/NFS_engine/nfs_stream_manager/wbp_ptr_s6[12] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sdram_port/sdram_dest/sdram_ddr_lb/cs_tmp_d_array_0[1] (0,

0) FF sdram_port/sdram_dest/sdram_ddr_lb/cs_tmp_d_array_0[1] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sdram_port/sdram_dest/sdram_ddr_lb/sa_1_tmp_d_array_0[7] (0, 0) FF sdram_port/sdram_dest/sdram_ddr_lb/sa_1_tmp_d_array_0[7] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT app_port/NFS_engine/last_rd_rtp_info[22] (0, 0) FF app_port/NFS_engine/last_rd_rtp_info[22] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sdram_port/sdram_dest/pci_starting_addr[6] (0, 0) FF sdram_port/sdram_dest/pci_starting_addr[6] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sdram_port/sdram_dest/sdram_ddr_lb/sa_1_tmp_d_array_0[8] (0, 0) FF sdram_port/sdram_dest/sdram_ddr_lb/sa_1_tmp_d_array_0[8] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT

toe_port/init_if/bridge_init_packet_fifo_if/hold_trans_status_master_abort (0, 0) FF

toe_port/init_if/bridge_init_packet_fifo_if/hold_trans_status_master_abort (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT app_port/NFS_engine/nfs_stream_manager/write_be_s8[4] (0,

0) FF app_port/NFS_engine/nfs_stream_manager/write_be_s8[4] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sync_bridge0_secondary_pci_set_master_data_parity_error (0,

0) FF sync_bridge0_secondary_pci_set_master_data_parity_error (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sync_bridge0_secondary_pci_set_received_system_error (0, 0) FF sync_bridge0_secondary_pci_set_received_system_error (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sync_bridge0_secondary_pci_set_received_target_abort (0, 0) FF sync_bridge0_secondary_pci_set_received_target_abort (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sync_bridge0_secondary_pci_set_received_master_abort (0, 0) FF sync_bridge0_secondary_pci_set_received_master_abort (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sync_bridge0_secondary_pci_set_signaled_target_abort (0, 0) FF sync_bridge0_secondary_pci_set_signaled_target_abort (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sdram_port/sdram_dest/sdram_ddr_lb/sa_1_tmp_d_array_0[5] (0, 0) FF sdram_port/sdram_dest/sdram_ddr_lb/sa_1_tmp_d_array_0[5] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT app_port/NFS_engine/nfs_stream_manager/checksum_s6[2] (0,

0) FF app_port/NFS_engine/nfs_stream_manager/checksum_s6[2] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT app_port/NFS_engine/nfs_stream_manager/wbp_ptr_s6[14] (0,

0) FF app_port/NFS_engine/nfs_stream_manager/wbp_ptr_s6[14] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT app_port/NFS_engine/nfs_stream_manager/wbp_ptr_s6[6] (0, 0) FF app_port/NFS_engine/nfs_stream_manager/wbp_ptr_s6[6] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT app_port/NFS_engine/nfs_stream_manager/wbp_index_s6[6] (0,

0) FF app_port/NFS_engine/nfs_stream_manager/wbp_index_s6[6] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sdram_port/sdram_dest/sdram_ddr_lb/cs_tmp_d_array_0[2] (0,

0) FF sdram_port/sdram_dest/sdram_ddr_lb/cs_tmp_d_array_0[2] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sync_bridge1_secondary_pci_set_detected_parity_error (0, 0) FF sync_bridge1_secondary_pci_set_detected_parity_error (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sync_bridge1_secondary_pci_set_master_data_parity_error (0,

0) FF sync_bridge1_secondary_pci_set_master_data_parity_error (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sdram_port/sdram_dest/sdram_ddr_lb/sa_1_tmp_d_array_0[10] (0, 0) FF sdram_port/sdram_dest/sdram_ddr_lb/sa_1_tmp_d_array_0[10] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sync_bridge1_secondary_pci_set_signaled_system_error (0, 0) FF sync_bridge1_secondary_pci_set_signaled_system_error (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sync_bridge1_secondary_pci_set_received_system_error (0, 0) FF sync_bridge1_secondary_pci_set_received_system_error (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT packet_fifo_rtp_wr_to_host/command_fifo/fifo_ram/r_wr_data[6] (0, 0) FF packet_fifo_rtp_wr_to_host/command_fifo/fifo_ram/r_wr_data[6] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT packet_fifo_host_to_fc/command_fifo/fifo_ram/r_wr_data[6] (0, 0) FF packet_fifo_host_to_fc/command_fifo/fifo_ram/r_wr_data[6] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sync_bridge1_secondary_pci_set_received_target_abort (0, 0) FF sync_bridge1_secondary_pci_set_received_target_abort (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sync_bridge1_secondary_pci_set_received_master_abort (0, 0) FF sync_bridge1_secondary_pci_set_received_master_abort (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sync_bridge1_secondary_pci_set_signaled_target_abort (0, 0) FF sync_bridge1_secondary_pci_set_signaled_target_abort (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sync_bridge1_secondary_pcix_set_split_completion_overrun (0, 0) FF sync_bridge1_secondary_pcix_set_split_completion_overrun (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sdram_port/sdram_dest/sdram_ddr_lb/cke_1_tmp_d_array_0[1] (0, 0) FF sdram_port/sdram_dest/sdram_ddr_lb/cke_1_tmp_d_array_0[1] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sync_bridge0_secondary_pcix_set_split_completion_discarded (0, 0) FF sync_bridge0_secondary_pcix_set_split_completion_discarded (0,

1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT

sdram_port/sdram_dest/sdram_ddr_lb/ddr_datapath[5].ddr_datapath/reset_strobe (0, 0) FF

sdram_port/sdram_dest/sdram_ddr_lb/ddr_datapath[5].ddr_datapath/reset_strobe (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sdram_port/sdram_dest/sdram_ddr_lb/cke_1_tmp_d_array_0[0] (0, 0) FF sdram_port/sdram_dest/sdram_ddr_lb/cke_1_tmp_d_array_0[0] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT app_port/host_int_out[1] (0, 0) FF app_port/host_int_out[1] (0,

1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT app_port/NFS_engine/nfs_stream_manager/wbp_count_s6[0] (0,

0) FF app_port/NFS_engine/nfs_stream_manager/wbp_count_s6[0] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT toe_port/toe_secondary_pcix_if/pcix_if/pcix_init_if/single_xfer (0,

0) FF toe_port/toe_secondary_pcix_if/pcix_if/pcix_init_if/single_xfer (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT fc_port/init_if/init_aggregate/xfer_byte_count[2] (0, 0) FF fc_port/init_if/init_aggregate/xfer_byte_count[2] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sdram_port/sdram_dest/sdram_ddr_lb/sa_1_tmp_d_array_0[1] (0, 0) FF sdram_port/sdram_dest/sdram_ddr_lb/sa_1_tmp_d_array_0[1] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sdram_port/sdram_dest/sdram_ddr_lb/ba_1_tmp_d_array_0[1] (0, 0) FF sdram_port/sdram_dest/sdram_ddr_lb/ba_1_tmp_d_array_0[1] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT app_port/NFS_engine/nfs_stream_manager/checksum_s6[6] (0,

0) FF app_port/NFS_engine/nfs_stream_manager/checksum_s6[6] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT app_port/NFS_engine/nfs_stream_manager/wbp_count_s6[2] (0,

0) FF app_port/NFS_engine/nfs_stream_manager/wbp_count_s6[2] (0, 1)

ERROR:Place - Due to placement constraints, the following 2 components cannot be placed. The relative offsets of the components are shown in brackets next to the component names. LUT sdram_port/sdram_dest/sdram_ddr_lb/ba_1_tmp_d_array_0[0] (0, 0) FF sdram_port/sdram_dest/sdram_ddr_lb/ba_1_tmp_d_array_0[0] (0, 1)

ERROR:Place:120 - There were not enough sites to place all selected components ERROR:Pack:1499 - The timing-driven packing phase encountered an error.

Section 2 - Warnings

-------------------- ...

**************************************************** END HERE ****************************************************

Sorry, I had a typo in my previous response. You need to run *without*

-timing, but with the chipscope cores, in order to get a utilization estimate with the cores in place. 88% is a relatively high utilization

- certainly not full, but not that far away from full either. I'd certainly hope that your chipscope wouldn't take up 3000 LUTs, but depending on your timing domains, I could see map getting into a bind with considerably less than 3000 LUTs.

Does the generator give you a size of your core (either saying it is x CLBs tall, or number of LUTs used)?

Have you tried removing a large block in your design to see if the ILA core will then fit?

-p

-o

know

The column called "CLB array" in the "Slice configurations" section of the Xilinx datasheets outline the number of CLB's each device is composed of (number of CLB's vertically vs. CLB's horizontally). Although they don't have to be, RPM's are usually arranged vertically, and it is possible for the RPM to exceed the available number of CLB's in one of the two directions. The 2VP30 has 80 CLBs vertically, which is quite a few.

Good luck,

Marc

It appears that something in your design is causing the LUT adjacent to flip-flop to be already occupied. I suspect it may be a global reset that isn't quite global which is forcing the synthesis to insert a gate between the LUT and the FF. Look carefully at the synthesized output to see if it is what you intended.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759

Thanks Ray for your comment.

How do you deduct from the error message the possibility of a gated reset ? and how could that be related to the addition of ICON and ILA cores ? that is the only "delta" from my "healthy" design ...

Ran

Something to try as a work around would be to lock the the Chipscope RPM down based on either the somewhat successfully non-timing driven run or based on your own judgment. The timing driven packer has some difficulty resolving the placement of RPMs, especially in the presence of area constraints and local clock placement requirements (will improve in 7.1i). With the RPM locked, the timing driven packer is likely to be successful and may resolve the congestion problems you're having with the non-timing driven flow.

Regards, Bret