XST is synthesising the following verilog code to a 8192x24-bit RAM.
module bram_8k (clk, addr, di, do); input clk; input [12:0] addr; input [23:0] di; output reg [23:0] do;
reg [23:0] ram [8191:0];
always@(posedge clk) begin ram[addr]
Because of comments from others on this forum, I've gotten into the habit of LOCing the BlockRAMs whenever relative placement is critical. While there might be a slightly "better" location for the BlockRAMs than what I choose, the place & route seems to do a better job filling the logic around the memory rather than trying to figure out a good placement for both logic and memory at the same time.
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