Verilog ASIC conversion to Xilinx FPGA - GOTCHA

Hi all,

Something that may be of interest when converting Verilog ASIC designs to Xilinx FPGAs. I noticed this when trying to convert a customer's ASIC design. When trying to set a clock to out constraint on an output that is being driven by an inout (see sample below), the place and route tool ignores the constraint, and gives the following msg:

WARNING:Timing:2667 - CLK does not clock data to metoo WARNING:Timing:2666 - Constraint ignored: TIMEGRP "metoo" OFFSET = OUT


//EXAMPLE CODE module test (CLK, RST, ENABLE, IN, BIDIR, METOO); input CLK, RST, ENABLE, IN; inout BIDIR; output METOO;

reg test_reg;

always @(posedge CLK or posedge RST) if (RST) test_reg

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Chris Smoot
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