hi,
i just noticed that the clock on the submodules of my top module is delayed (about 1,3ns) with respect to the clock on the top module. im new to xilinx FPGA's and ISE so i might be forgetting something?? maybe DCM??, i use only VHDL entry so i havent instantiated any, should i? im using xc2v4000 and ISE 5.2i i think thanks