Hi,
If anyone from Xilinx is listening, would they consider changing TSMCCCS (hold time of CS_b from CCLK rising in SelectMAP mode) to
-0.5ns or so? TSMCCCS is currently 0.0ns in V2P and +1.0ns in older parts.
This change would enable CS_b and CCLK to be tied together on the board, which simplifies certain applications which involve the FPGA being configured from a CPU, with CS_b and CCLK both coming from the same output of a chip select decoder. CS_b and CCLK aren't close on the package, and 0.5ns would be sufficient to allow for delays on the PCB between the two pins. (Perhaps CS_b and CCLK could be moved closer together? This would also help signal integrity.)
I recently saw a design using a SpartanIIE (which requires +1.0ns of hold time) that had an RC network on the board to provide the delay.
Thanks, Allan.