Xilinx: infering dual port ROM in VHDL


im having trouble infering a dual port ROM with xilinx ISE 5.2i. I can infer dual port RAM, but i need it to be ROM in order to have it initialised. does anybody know how to do it? i've been searching the web and xilinx website, but i havent seen how to infer a dual port ROM, only regular ROM, but i need to do two read access (and given that the ROMs will be implemented in BlockRAM, it'd be a waste if i had to use two cycles to read from dual port capable BlockRAMs) i'd like the approach to be VHDL, cause it seems that you can do it with Coregen?? but i want it to be VHDL cause the ROM generation has to automatic (thru a C program that generates VHDL code) comments are welcome, TIA

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It does not have to be ROM to be initialised. I usually use constraints editor or go directly to the ucf file to set the RAM/ROM initial values. The blockram can be considered as writeable ROM that simply isn't written. Usually I tie off the write enable to the inactive state if it really matters but more often being able to split the blockram into a combination of RAM and pseudo ROM is more useful to me.

John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board.

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This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted.

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John Adair


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