do DDR SDRAMs have CPs ?

Hello all,

Does anyone know if DDR SDRAM modules (or similar modulars) use internal charge pumps (to boost up the power supply of core modules)? The reason why I ask is that I am interested in DDR SDRAM's leakage current values. Someone mentioned (in another ng) that there may internal charge pumps. Hence, if there is a CP in the DDR SDRAM, killing the clock and grounding/vdding all other data inputs will not

*make* the leakage current drop to the *correct* order of magnitude, if the CP is enabled and has its own local (ring) oscillator. *Correct* order of magnitude (for a typical IC) being sub-uAs.

If anyone knows of a typical value of the LEAKAGE CURRENT of DDR SDRAM module, it will be much appreciated. In datasheets, I was only able to locate the MAXIMUM INPUT LEAKAGE CURRENT parameter ([-5uA to +5uA]).

P.S If a DDR SDRAM DIMM has 184 pins and most of the pins are data pins, then the TOTAL INPUT LEAKAGE CURRENT can accumulate up to ~920uA (theoretically). This is a pretty impressive leakage conssumption! Can this be rigth ?

Please advise

-Roger

Reply to
Roger Bourne
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P.P.S DDR SDRAMs have internal PLLs to redrive the CLK

Reply to
Roger Bourne

I'm not in the SDRAM business, so take this with a grain of salt.

Charge pumps are normally only used in floating-gate devices (FLASH, EEPROM, ), where it is required to tunnel charge into the gate. This takes a higher voltage.

Leakage is unrelated to the presence or absence of a charge pump. It depends on the technology node and on special measures taken by the manufacturer (e.g. dual-gate transistors). As a rule of thumb, the leakage at 90nm is three times worse than at 130nm. I don't think SDRAM has made it to the 64nm process node yet.

The crossover where leakage and dynamic power are equal is somewhere around the 90nm node. Baring any special tricks, I'm guessing that current DIMMs have around 500mA leakage power consumption.

You can probably measure the leakage by powering the DIMM without providing a clock. You may have to start a transaction and stop midway to go around some power saving tricks.

Kind regards,

Iwo

Reply to
Iwo Mergler

You mean "500uA" rigth ? It was a typo. It has to be a typo! (By DIMM, you mean a common DDR SDRAM 184-pin DIMM card, rigth ?)

-Roger

Reply to
Roger Bourne

Not so unlikely. A 512 MB DIMM has 4G transistors in the memory array alone. Add to that sense amps (gated power), drive and decode, and control logic, and you have a whole lot more transistors than a modern CPU. And modern CPUs have quite the leakage - multi amps.

And yes, DRAM chips have internal voltage regulators. Don't know if those are charge pumps, but it seems that it is sometimes desirable to change power supply voltage from the JEDEC standard. ISTR that it was a lower voltage that was needed, so likely just a pass transistor.

And there is more: I just read PC memory controllers use 'thermal throttling'. How and when is unclear, but it seems to be 'better' not to run the chips at full tilt all the time.

Thomas

Reply to
Zak

Yes, but most are isolated and drawing no power at all. Dynamic memory isn't anything like static ram where every cell is connected to power.

Reply to
AZ Nomad

It's half an amp, I'm afraid. In fact, my estimate was probably optimistic. Looking at the datasheet of a Samsung 1GB DIMM (M312L2923BG0), the power consumption is between 510mA and

4100mA at 2.7V. The 510mA is in what they call "low power mode", probably with most of the leaky stuff switched off.

See it this way: A pentium4, using a 130nm process takes about

20W of power with the clock off. It's got about 1000 times less transistors (but much faster ones).

Kind regards,

Iwo

Reply to
Iwo Mergler

Is that a single sided or double sided DIMM? "Low power mode" also is likely still refreshing so not really all "leakage".

Not only faster transistors, but leaky ones and connected across the rails. It's also one chip, instead of 8-18 (as your DIMM is).

--
  Keith
Reply to
Keith

It's two banks. Refresh interval time is given at 7.8us. I think those ~130KHz can be ignored for dynamic power considerations.

Here is the (randomly picked) datasheet I am looking at:

http://210.118.57.197/Products/Semiconductor/DRAM/DDRSDRAM/DDRSDRAMmodule/RegisteredDIMM/M312L2923BG0/ds_m312l2923bg0_rev10.pdf

I was only using a DIMM as an example because Roger said something about "memory module". The leakage current scales linearly with the number of chips used. ;^)

Kind regards,

Iwo

Reply to
Iwo Mergler

I assume you mean "ranks" (16 or 18 devices).

That's for *each* row! How many rows?

http://210.118.57.197/Products/Semiconductor/DRAM/DDRSDRAM/DDRSDRAMmodule/RegisteredDIMM/M312L2923BG0/ds_m312l2923bg0_rev10.pdf

Well, that much is true. ;-)

--
  Keith
Reply to
Keith

The two 'sides' of the module are in a banked arrangement.

The single/double sided thing is purely the choice of the PCB layout person. You could place 4 8bit chips on each side without making it a 'double sided DIMM'.

In this case, 8192. The interval time is the maximum time between refreshing two consecutive rows. Refresh for any cell is around 60ms.

Kind regards,

Iwo

Reply to
Iwo Mergler

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