Can someone help me interpret the following Virtex2 TRCE report please? Why is it saying the BUFG output has both period and offset unconstrained? It seemed to push my period constraint through the DCM just fine as coverage is
90%; so why would it say my BUFG output has unconstrained period analysis?.
My project is connected in a fairly standard way basically consisting of a non-clock pin into IBUFG into a DCM. The CLK0 of that DCM gois into a BUFG. The output of that BUFG goes back to the feedback on the DCM as well as thousands of other places including RAMBs, FFs, and one OBUF/PAD combo.
Thanks for any help. I'm using Xilinx 6.1.2. You may have to paste this into a fixed-width font.
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