This uses an FPGA LVDS input as a comparator, and one external RC, to make an ADC. Just need an algorithm to process the flop output.
A simpler ADC should be possible.
Version 4 SHEET 1 880 680 WIRE -16 0 -112 0 WIRE 48 0 -16 0 WIRE 160 0 48 0 WIRE 416 0 240 0 WIRE 480 0 416 0 WIRE 528 0 480 0 WIRE 416 48 416 0 WIRE -112 64 -112 0 WIRE 96 112 64 112 WIRE 128 112 96 112 WIRE -112 160 -112 128 WIRE 64 160 64 112 WIRE -16 176 -16 0 WIRE 16 176 -16 176 WIRE -48 224 -112 224 WIRE 16 224 -48 224 WIRE -112 256 -112 224 WIRE 64 272 64 240 WIRE 272 288 208 288 WIRE 368 288 368 224 WIRE 368 288 272 288 WIRE 416 288 416 224 WIRE 480 288 416 288 WIRE 512 288 480 288 WIRE 208 336 208 288 WIRE 416 336 416 288 WIRE -112 384 -112 336 WIRE 208 448 208 416 WIRE 416 448 416 416 FLAG 416 448 0 FLAG 208 448 0 FLAG 64 272 0 FLAG 96 112 R FLAG -112 384 0 FLAG -112 160 0 FLAG 272 288 D FLAG 480 288 CLK FLAG 480 0 N FLAG 48 0 F FLAG -48 224 IN SYMBOL voltage -112 240 R0 WINDOW 0 48 44 Left 2 WINDOW 3 41 78 Left 2 SYMATTR InstName V1 SYMATTR Value 0.75 SYMBOL Digital\\dflop 320 144 R270 WINDOW 0 40 -49 VRight 2 SYMATTR InstName A1 SYMBOL voltage 416 320 R0 WINDOW 0 56 49 Left 2 WINDOW 3 45 90 Left 2 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V3 SYMATTR Value PULSE(0 1 0 0 0 1u 10u 1e6) SYMBOL bv 208 320 R0 WINDOW 0 -97 53 Left 2 WINDOW 3 -212 93 Left 2 SYMATTR InstName B1 SYMATTR Value V=1+tanh(V(R)) SYMBOL e 64 144 R0 WINDOW 0 53 50 Left 2 WINDOW 3 54 84 Left 2 SYMATTR InstName Elvds SYMATTR Value 1000 SYMBOL res 256 -16 R90 WINDOW 0 65 53 VBottom 2 WINDOW 3 69 56 VTop 2 SYMATTR InstName R1 SYMATTR Value 10K SYMBOL cap -128 64 R0 WINDOW 0 46 12 Left 2 WINDOW 3 45 48 Left 2 SYMATTR InstName C1 SYMATTR Value 1µ TEXT 558 200 Left 2 !.tran 10m TEXT 512 80 Left 2 ;Cheap FPGA ADC TEXT 528 128 Left 2 ;JL Jan 17 2022