Bit banging for 8051, SPI

Do you mean as a SPI Master, or a SPI Slave ?

-jg

SPI is dead simple to implement in software as a master. Where are you getting stuck?

--
Rich Webb   Norfolk, VA

Hi,

I am interested in SPI Master for an 8051

Thanks,

Methi

Hi,

I was trying to use the SPI interface in 8051 but am not getting the rquired output.

So I thought I shall try bite banging instead...

Was wondering if I would get some ideas...

Thank you,

Methi

In article , methi writes

Which 8051 device are you using, standard 8051 does not have an SPI interface? to what SPI slave device?

--
Tim Mitchell

Hi Tim,

I am using Cygnal's C8051F022 which has an SPI interface.

I am using a three-wire transfer mode with the lines MOSI,SCK and MISO.

My SPI slave is an FPGA.

Thank you,

Methi

Tim Mitchell wrote:

So can you describe what you are doing now, and what is happening (or not happening)?

--
Tim Mitchell

I've bit-banged it on a Cygnal C8051F061 and as Rich Webb said earlier it is funnybook simple. My guess is that it should be even easier using the on-chip SPI hardware. Look for App notes on Silabs.com and user discussion on

forums.

Bob

Hello,

I actually tried using the SPI interface in the micro itself..But I am not receiving the right data on the MOSI line...The SCK is fine...its

110.6khz..... My slave which is an FPGA takes in the serial data and converts it into parallel...The FPGA is working fine..

I have initialized my SPI registers, port 0...etc..

I am right now sending two bytes of data....one following the other to the slave..

When I probe my MOSI line, I see the wrong data being sent to the FPGA..

SO I thought that I will instead go for the BIT BANGING method....

Thank you,

Methi

Tim Mitchell wrote:

Hi Bob,

I have posted this message earlier in the comp.arch.embedded group...This is what I tried doing with the SPI interface available in

8051...

My F022 acts as the SPI master.I have the register h5 whose value changes from time to time. Every time its value changes, I need F022 to transfer one 8 bit value(03h) to the slave followed by the 8 bit value of h5.

My code for doing that is as follows:

Its a subroutine which is called everytime the value of h5 changes

fpga_talk: clr fpga_cs_1 (select the slave) mov spi0dat,#003h ( move 03h and start the transfer) wait_here1: jnb spi0cn.7,wait_here1 (wait till transfer is completed) clr spi0cn.7 (clear the bit) mov r7,spi0dat (move the data sent by the slave to R7) lcall delay_spi (call a small delay for 1ms) mov spi0dat,h5 (move the h5 value and start the transfer) wait_here2: jnb spi0cn.7,wait_here2 clr spi0cn.7 mov r7,spi0dat setb fpga_cs_1 (de-select the slave) ret (return from subroutine)

My SPI is intialized as follows:

mov p0mdout,#015h ( port configuration)

mov spi0cn,#003h ;SPI Control Register mov spi0cfg,#007h ;SPI Configuration Register mov spi0ckr,#063h ;SPI Clock Rate Register

My sysmtem clk is intialized as follows:

mov oscxcn,#067h ;External Oscillator Control Register clr a ; osc djnz acc,$ ; wait for djnz acc,$ ; at least 1ms

ox_wait: mov a,oscxcn jnb acc.7,ox_wait ;poll XTLVLD

mov oscicn,#008h ;Internal Oscillator Control Register

As far as I know, these are initialized correctly

My XBRx registers are as follows:

mov xbr0,#006h ;XBAR0: Initial Reset Value mov xbr1,#014h ;XBAR1: Initial Reset Value mov xbr2,#040h ;XBAR2: Initial Reset Value

My XBARE bit is set to '1' which means that SPI is enabled.

On going through the examples in one of the application notes of Cygnals:AN128, I have noticed the following:

The XBR0 register is initialized with the value:

XBR0 = 0x0F; // skip SPI pins in XBAR

Should I be doing the same?

And also I havent connected the NSS pin ( pin 57 which is P0.5 to my slave)

What I am right now seeing is that my master ( F022) is sending the 2 bytes of data ( 03h,01h) for 16 clock cycles.

01h is the first value h5 takes.

And then it sends 00h,00h for the next 16 clock cycles.

This is again followed by 03h,01h for the enxt 16 clock cycles.

I dont want this to happen.I just want it to transfer it once.

Also another problem is that when the value of h5 changes, I am calling the subroutine again for another transfer...

I notice that even though its the same subroutine, there is no sck or anything happening

Any ideas...

Thankyou, Methi

You need to control the slave select (SS-) line to synchronize the slave before the transfer.

--

Tauno Voipio
tauno voipio (at) iki fi

Hi,

I have not connected the NSS line write now...

But you are say> methi wrote:

I also have another question

The SPIF bit is set to logic 1 everytime a data transfer is complete..

When interrupts are enabled, setting this bit causes the CPU to vector to the SPI0 ISR.

I dont have any SPI0 ISR written...so what does this mean?

Thank you, Methi

Hi,

I have tried sending data from 8051 to the fpga using the Bit banging method as follows:

This is a subroutine that I am calling everytime my H5 value changes:

fpga_talk: clr fpga_cs_1 mov a,h5 mov r7,#008h rlc a spi_loop: mov p0.4,c setb p0.2 mov c,p0.3 rlc a clr p0.2 djnz r7,spi_loop mov r7,a setb fpga_cs_1 ret

I have also disabled the on chip SPI interface.

Still I dont seem to be seeing any clock at the sck line at p0.2

I dont know what I am doing wrong...

plz help...

thank you, Methi

methi wrote:

Yes it is absolutely critical that you follow the XBAR priority requirements to the letter. Otherwise it will definitely not work. I don't have the F022 data sheet here, but read that section carefully and make sure you have assigned all of the port bits' special functions properly.

Bob

and how many clock pulses ?

'Wrong' meaning what ? - no data at all, or reversed bit data, or wrong baud rate, or data that is mangled by sending the second byte too soon...

A very simple 100% spin test for SPI, is to wire an external inverter MOSI/MISO, and confirm after each completion, that RX data is inverted TX.

-jg

Its 16 clock pulses

Wrong data in the sense...

Every alternate bit is reversed

And it doesnt stop with 16 clock cycles..

It generates another 16 clock cycles with all logic '0''s.

Thank you, Methi

Jim Granville wrote:

Since this is not working.....

I tried the bit banging method...where I have disabled the SPI by moving data

mov spi0cn,#002h

This disables the SPI on the chip...

And then I configured the Port 0 pins as follows:

mosi bit p0.4 miso bit p0.3 sck bit p0.2

And then in my program,I am calling the foll.subroutine:

fpga_talk: clr fpga_cs_1 mov a,h5 mov r7,#008h rlc a spi_loop: mov mosi,c setb sck mov c,miso rlc a clr sck jmp spi_loop djnz r7,spi_loop mov r7,a setb fpga_cs_1 ret

this doesnt seem to be working either...

What other registers should I modify in order to make this work

My port0 output config register is as follows:

mov p0mdout,#015h

plz help...

thanku, Methi

methi wrote:

Wow - It is very hard to imagine a failure mode that would do that. Check the device errata, but it would be _very_ hard to do this by accident in silicon! Suspect operator error - what patterns did you use ?

anything inconsistent like this screams SW oops, not HW. If you see correct length data, and clocks, that suggests the port and SFR setups are OK,

You should connect MOSI to MISO, and read back single bytes, with a rolling test pattern. First use a SW delay to space the Bytes, then use the SPIF or ==, and check it works the same.

-jg