I thought just for fun let me try to digitize some video using the input comparator. I am stuck with 3.3 V I/O on Spartan 2 because of the proto board... So then CTT works on 3.3 V and 1.5 V rteference, should do something with 1.5 V signal...
But now the problem:
ERROR:Place:1747 - The IOB video_in is locked to site P110 in bank 3. This true
violates the SelectIO banking rules. Other incompatible IOBs may be locked to the same bank, or this IOB may be illegally locked to a Vref site. Please ? of cause they may be, but they are not...
consult the SelectIO application node. where would that be?
ERROR:Place:993 - Due to Virtex SelectIO banking constraints, the IOBs in your design cannot be automatically placed. It's a Spartan 2, not a Virtex...!
I did: // For the r2r ladder that drives the Vref is here: OBUF_CTT da0(.I(da_output[0]), .O(da_out[0]) ); OBUF_CTT da1(.I(da_output[1]), .O(da_out[1]) ); OBUF_CTT da2(.I(da_output[2]), .O(da_out[2]) ); OBUF_CTT da3(.I(da_output[3]), .O(da_out[3]) ); OBUF_CTT da4(.I(da_output[4]), .O(da_out[4]) ); OBUF_CTT da5(.I(da_output[5]), .O(da_out[5]) ); OBUF_CTT da6(.I(da_output[6]), .O(da_out[6]) ); OBUF_CTT da7(.I(da_output[7]), .O(da_out[7]) );
// The video is on the other side of the comparator... IBUF_CTT vidin(.I(video_in), .O(inbit) );
In the constraints file the ports are specified as normal. All these pins (and no other) are on bank 3. So what do I do wrong?
Must be some silly thing... Simulation works fine, 8 bits video, 100 MHz clock, should at least do something..
OK, now it works, problem with webpack is it so often gives wrong messages, now it gave a correct on (I was using a pin differently) and I did not believe a word it said anymore.. So, the 1.4 V pp input video on a CTT pin with 3.3V supply. A r2r ladder on the comparator reference. A 8 step successive approximation, that looks at 0 / 1 from the input (video lower or higher then reference) gives 8 bit video. Because I only use 1.5 of 3.3V it is now 7 bits.. this can be changed. First thing was my DVD player, and is in color, even with 50 MHz clock. But VERY noisy, really bad... plenty of detail RF parts. But this noise, I think maybe the reference or comparator switch level is affected by everything else happening in the FPGA? I test with a second r2r ladder as DA to the output. Anyways, will try some more later, see if this can be made noise free? External comparator perhaps? Will see. I have biased the CTT at 1.5 V and AC coupled the video in. JP
Random suggestions follow - you've probably thought about most of these already, but I'll offer them anyway :-)
Do you *know* where the ground reference is that's used for the output pads that drive your R2R ladder? have you taken care to use output pads all in the same bank for that?
Could you consider adding a second R2R and digitizing the video GROUND, also AC coupled in? Then subtract VideoGnd from VideoHot, add a suitable offset (presumably you're getting the offset by sampling the back porch somewhere?). This *might* help if both R2R DACs are driven from buffers that share a common ground, i.e. are very nearby on the chip.
I've seen 7-bit SNR with very simply constructed R2R DACs on the output of FPGAs before now, but that was at quite low frequencies so the FPGA itself would have been much quieter. I say this because 7-bit should be plenty to get reasonably quiet-looking video.
Finally, are you sampling a composite NTSC or PAL video signal? If so, what's happening about aliasing of the colour subcarrier? Wouldn't it be a good idea to sample at an exact multiple of Fsc?
On a sunny day (Wed, 12 Nov 2003 18:34:09 -0000) it happened "Jonathan Bromley" wrote in :
Nice to get some suggestions!
Yes, and today I used a separate bank for the DA output and the comparator, so I could use TTL like output to the DA (and not have to use the same input type). I also tried all other comparator input modes.
Yes, this 'differential' but probably not really needed for what I want it for.
I disabled some other circuits on the board, that improved things. So, ground loops...
Yep, many, many years ago I was at a research institute in Amsterdam, You were allowed to spend 10% of the time on your own project / idea... Good place, was in the front of things. Anyways I designed a digitizer with 6 bits and digitized my first video there in 1979. Big eurocard full of chips, people standing around it ..oooh... Next day guy walks in, drops data sheet on my desk of 8 bit flash AD chip. hehe
Good point, yes the idea is (if this works as expected) to digitize RGB from a DVD player, then store a line in block RAM in FPGA, read it out at twice the speed, and stick it in a normal VGA monitor (at 31kHz
50 Hz). I have a card from Philips that does exactly that (with normal logic), but it is an old ISA card...., not very good quality either (PCTV1000). So I want something like that.. Then of cause the mpeg2 coding, but alas, first the digitizer.
If this code works the way I want, I will set up a webpage. Today I played some more, but have things to do, so it will take time. Anyways I slowed down the clock, to be better able to see what happend (100x slower), an it seems something strange happens in that input comparator. I can see my algo working, but about say 1 in a 100 times or so it gets 100% the wrong (just any) value. Simulation is OK, and using extra registers and delays makes no difference. What DOES make a difference is when I hold my finger on the reference input. This points to some oscillations perhaps... Maybe it it is picky about rise times.... these will by definition be slow on the last steps (just add or subtract a few mV). Then I tried to drive it with 50 Ohms, but no real difference. So, more play later. OK, this test is with a composite PAL signal, and if I was to use composite, then digitizing at 3 x 4.43 MHz PAL subcarrier would be good (so no moving interference etc..) That gives 13.29 MHz, 8 steps = 106.32 MHz clock. This could be a nice LC oscillator, divider in FPGA, lock to 4.43 source, use varicap to tune 100 MHz oscillator.. With all that color and TV stuff I am in my element, no problems there. I will try some more later, perhaps Saturday, sure I will post it here when it is usable. Actually I did watch part of a DVD with it... in color too.
You can wonder, why not use the flash AD chips with 4 input mux... I have one... But this is just for fun. And 16 resistors are cheaper then that chip? I did DA in 1979 with 8 resistors, 1k 2k 4k 8k etc.. Ends connected together.
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