Clock signal for an external peripheral

It doesn't really matter how you create it.. as long as its in the right phase for what you need to do... just try to avoid outputting the output of a GBUF. I think the best output is a divide of one of the system (internal)clocks.

Simon

Sorry Simon, but I don't have understood.

Could you explain please?

Thanks Marco

There are three things here.. what don't you understand?? They are both basic concepts

What's so hard about any of those ? If you are finding English difficult.. I would suggest finding a translator :-) If you don't understand the basics of digital logic.. get a book and learn... FPGAs are no different to a PCB with its logic... only its smaller, faster and bugs are easier to fix. (mostly)

Simon

(internal)clocks.

I have some troubles with english... sorry. Google translator is not very good.

If I have understood I must avoid using a GCLK out pin.

Instead I can use which pin I desire, right?

Clock frequency is not a trouble.

Many Thanks Marco