Hello, I have written a program to run on the Celoxica RC100 board and compiled it to edif file. When i use the Xilinx Design Manager to convert it to a bit file, it always fail during the mapping stage saying it cannot fit into the device. I have tried many optimzation method in the DK1 suite and nothing works. Tried using its technology mapper (take very long to compiler) also cannot work. And it always exceed the maximum slices and 4 i/p look-up table (both exceed by 50%). I have tried the -r option in the mapping and it still exceed.
I'm using the following software, Celoxica DK1 Design Suite 1.1 Service Pack 1, compiler version 3.1.2676 Xilinx Design Manager Revlease version 3.3.08i, application version D.27
Thanks you from Triax