I wish to generate a frequency of approx 400 Hz using Xilinx Spartan II(200 MHz)and send the 1 bit signal to a speaker output and hope to hear some noise. My VHDL code, tested on PeakVHDL simulator does generate the waveform and is pasted at the far bottom. The problem is that the code does not compile on Xilinx because "WAIT for 2.5 ns" is not supported on Xilinx Spartan II for a process. What would be the simplest way out to generate 400 approx Hz on a Xilinx 200MHz device? I have used200MHz/(2 to the power of 19) = 382 Hz approx. (Use MSB of 19 bits of STD_LOGIC_VECTOR)
Another thing which has confused me is: If I wish to write an entity(below) for Spartan II, does the programmer worry about generating the signal for "clk" input? Or simply connect it to the correct pin of FPGA and I should get the signal of 200MHz?
ENTITY some_entity IS PORT (clk : IN BIT); END some_entity;
For my code tested on PeakVHDL, I have generated the 200MHz signal using a test bed(music_tester) and then modified it to 400Hz.
I apologise if the question is basic.
Thanks in advance
ENTITY music_tester IS PORT (clk : OUT STD_LOGIC; freq : IN STD_LOGIC); END music_tester;
ARCHITECTURE behavioral OF music_tester IS BEGIN process BEGIN clk