I've got a beginner question concerning instantiating RAM inside a Spartan II XC2S50 using WebPack. When attempting something like the following:
type ram_array is array(0 to memsize-1) of std_logic_vector(width-1 downto 0);
the HDL synthesis reports using a 8-bit 1024-to-1 multiplexer. Is the synthsizer trying to build the RAM out of flipflops? Should I build my RAM out of ram32x1s type primitives instead?
-- Joe Lawrence take out the ZZ's for email
your type declaration looks okay, so it's probably a problem with the "process" statement where you're using the signal of type "ram_array." could you post that code up?
try searching for "inferring ram" in XST's user manual or on xilinx's web site. they should give you a template of how to word your VHDL such that XST can properly infer your ram.
--Vinh
Thanks for the tip, I found a synthesis guide on the xilinx website that provided me with the information I needed.
-- Joe Lawrence remove the zz's for email
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