I've got a strange problem that I don't know any solution for - up to now I tried everything, but it didn't work. The state machine always stops to go to the next state - I really don't understand why.
I've got a state machine with 5 states: SEL_EP, WRITE_INIT, WRITE_DATA, VAL_BUF and IDLE. It gets stuck after the WRITE_INIT state, just remains in the WRITE_INIT state all the time. WHY???? The 2nd (smaller) problem is, that the data at write_out comes one clock cycle too late. I understand why, but how can i change this?
I don't know if it's a good idea to solve my problem with my kind of code, i'm an "advanced beginner" and as I am used to program "sequential programming languages" I've got big problems with doing sequential things in vhdl. What is the easy way to do things one after the other, e.g. write one byte after the other? (also to be synthesizable).
I put the code at
Please help me! I really don't know where to go on.
Thank you, Simone