Why not DDR in FPGAs?

Hi all, here is a quit simple, general question: Why do the FPGAs (as fare as I know) not use Double Data Rate on Chip for their FlipFlips?

  • This would reduce the power for the clock tree.
  • I could directly use the Data from an external DDR-DRAM
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itsme
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I have not tried this with Synplicity yet. With XST the Coolriunner dual edge flip flop is inferred with the following VHDL construct:

process(vclk) begin if (vclk'event) then ... end if; end process;

Which is exactly as one would expect. To get this inference to work, if running XST with a script, the part type has to be set to XBR rather than XC2C64 (as one would expect from the documentation). The flow engine sets the part type correctly.

Regards, Erik Widding.

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Birger Engineering, Inc. -------------------------------- 617.695.9233
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Erik Widding

The Xilinx Spartan-3, Virtex-II, and Virtex-II Pro FPGAs have DDR registers as part of each I/O block.

For high-performance applications, you would want to use two outputs from the Digital Clock Manager, one being the de-skewed, non-shifted clock output and the de-skewed, 180 degrees phase-shifted clock output. This technique minimizes any potential duty-cycle distortion and gives you most of the entire half-period for your logic application.

You might take a look at the following web site as it contains both application notes and sample code.

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Steven K. Knapp
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Steven K. Knapp

I think the origional poster means the opposite, having the internal registers in teh FPGA trigger on both the rising and falling clock edge, to save power in clock distribution.

Unfortunatly, this would require even clock phases in all cases, significantly more complex flip-flops, and I'm guessing the power-savings in the clock distribution (now running at half speed) would be swamped by the additional power draw within the flip-flops themselves to allow them to trigger on both edges.

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Nicholas C. Weaver                                 nweaver@cs.berkeley.edu
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Nicholas C. Weaver

... but takes twice as many BUFGs.

Feature request: more BUFGs.

Grip: differential clocks take two global clock pins. It would be better if they took one global clock pin and the other pin in the differential pair was a standard I/O pin. I don't know if that is feasible, but differential clocks chew IBUFGs quickly.

On the project I'm currently working on we ran out of global clock pins this way and put one of our clocks on a non-global pin. Works fine. Our experience shows that it's preferable to have differential clocks even on non-clock pins than to use single-ended clocks.

Hamish

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Hamish Moffatt VK3SB
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hamish

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