Hello, I am developing a solution using Xilinx ISE 8.2 and Modelsim
6.1. When I start the Post Place & Route simulation, I receive many warnings, since at the beginning some signals are in a incoherent state, like the Digital Clock Manager which is not locked yet.
I would like to know what the experts do when they simulate complex circuits. Do you ignore those warnings? Do you try to eliminate them? Is there any way to filter innocuous warnings?
Regards.
PD: these are some of the warnings I receive:
# ** Warning: /X_FF HOLD High VIOLATION ON I WITH RESPECT TO CLK; # Expected := 0.042 ns; Observed := 0.025 ns; At : 1.397 ns # Time: 1397 ps Iteration: 3 Instance: /tim_top_tb/i_tim_top/g_dsp_n_1_i_dsp_n_g_global_bus_i_global_bus_link_i_global_bus_v241i875_q7
# ** Warning: CAS# Setup time violation -- tCMS # Time: 5 ns Iteration: 1 Instance: /tim_top_tb/dspa_sdram0_inst # ** Warning: RAS# Setup time violation -- tCMS