Dear all, I've placed my design in an Altera Stratix and use a PLL for clock generation. In a first stage PLL generated 22 MHz as output freq and Quartus II (3.0 release) showed 36 MHz as fmax. Due to this result, I have decided to increase PLL output to 33 MHz (without any change on the design). Now, after placement, Quartus Timing Analyzer shows 33.1 MHz as new fmax. I've repeated both placements (with a 22MHz PLL and with a 33 MHz PLL) multiple times and the results are similar.
Has the PLL configuration any impacts on other parameters which affect timings ?
I've also tried a backannotation when going to 33 MHz, but the results are the same. I can't use Chip Editor, since it crashes.
Thanks for your help.