Need help: Altera ALTPLL_RECONFIG state machine construction

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I've asked for help once before on this topic and was directed to look
at Ap Note #367.
Unfortunately, when I unzip the example designs, I didn't find a
walk-through or readme
file that describes how to go through each example (am I missing

I am using a Stratix II part and need to be able to monitor a input pin,
after power-up/
reconfiguration is complete, to switch between two different sets of
dividers (this pin
will tell the FPGA that one of two input clocks are going to be used).
From Ap Note 367
and the ALTPLL_RECONFIG Megafunction User's Guide, it appears that this
state machine/logic needs to determine if a reconfigure is required and
if so, issue a 1 clock
pulse on the reconfig pin of the ALTPLL_RECONFIG line, wait for the
reconfiguration to
be done, and then issue an asynchronous reset.  (The asynchornous reset
also needs to be
sent even if the reconfig is not needed).

None of the documentation that I've seen so far shows examples on how to
do this.  I've
seen included drawings that just show interconnection between the
and ALTPLL -- nothing else is given.

Does anyone have a step-by-step example with code and/or drawings that
explains how
to really design with the ALTPLL_RECONFIG and ALTPLL megawizard

Re: Need help: Altera ALTPLL_RECONFIG state machine construction
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Hi Bob,

Here is some info from our PLL applications team that hopefully helps

See the Stratix II errata for information on cases when you should
reset the PLL after a PLL reconfiguration:

Under "Stratix II FPGA Device Family Issues", see "PLL Reconfiguration
Issue".  It describes several scenarios and in which cases a PLL reset
is required, as well as how long the reset should be held, etc.  This
information has not been fully updated in the Application Note.

Aside from how to apply areset, the best places to look for info on
PLL reconfiguration are:

In AN 367, the section titled "Reconfiguring the C0 Counter" gives a
step by step description of how to reconfigure the PLL to change the
C0 clock output.  The first design example is essentially a design
setup with the simulation vectors to show this process:

The Stratix-II clock and PLL HandBook chapter describes what the
various counter settings mean and how different settings result in
different multiply/divide values.  See the "Hardware Features" section
entitled "Clock Multiplication & Division":

Hope this helps,


Vaughn Betz

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