I am having problems simulating fifos with quartus and modelsim. My environment is set up as follows:
Quartus II v4.1 SP1 Modelsim-Altera 5.8c (with updated sim models)
I was seeing problems on a large design I have, whereby the the data was not coming out of the fifo when being read. As this was a large desing I decided to create a new project/design which contains ONLY a fifo (LMP_FIFO+, single clock) and simulate that. I have generated the .vho file for use with Modelsim-Altera and simulated this with my own testbench.
One thing worth mentioning is that when I start the simulation, I get a load of warnings from Modelsim:-
** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0. # Time: 0 ps Iteration: 0 Instance: /fifo_test_tb/fifo_test_i0/fifo_i0/scfifo_component/auto_generated/dpfifo/fiforam/segment_a0_a_a0_a...this is just because I haven't specified an .init file for the fifo, but this won't prevent correct operation...will it ! ?
When I bring up the waves I can see the following:-
(i) the clock is running
(ii) reset, devpor, devclrn are all asserted (correct polarity) at start of the sim and then de-asserted 100 ns later.
(iii) the wr_req is set active, and the data_in has an incrementing pattern
(iv) valid_wrreq (internal to the LPM_FIFO+ component) is active as expected
(v) ww_fiforam_wraddress (internal to the LPM_FIFO+ component) increments as expected
(vi) fifo_usedwd (internal to the LPM_FIFO+ component) increments as expected
(vii) empty and almost_empty (internal to the LPM_FIFO+ component) get cancelled as expected
(viii) rd_req is set active
(ix) valid_rdreq (internal to the LPM_FIFO+ component) is active as expected
(x) ww_fiforam_rdaddress (internal to the LPM_FIFO+ component) increments as expected
(xi) fifo_usedwd (internal to the LPM_FIFO+ component) freezes since I am writing and reading at the same rate as expected (only start read once fifo_usedwd reaches about 12)
(xii) BUT, no data appears at the output port, even though everything else suggests that the fifo is being operated correctly !
Can anyone offer any assistance (I have also submitted a service req to Altera, but on previous experience am not to confident in the response I 'might' receive)
Any assistance would be very much appreciated
JohnnyNorthener