Altera Cyclone II DQ/DQS pins location

Hello group,

I have an issue with porting my high-speed DDR interface to Altera Cyclone II device. As far as datasheet says, Altera Cyclone II device does not have any dedicated circuitry to support DDR signaling in its Input/Output blocks for DQ pins. The only thing present in hardware is the clock delay circuitry on DQS pins. All other DDR logic is implemented using LUT's and triggers from adjacent Logic Array Blocks. So, it seams that we have only DQS pins location fixed, whenever all other DDR pins may float within the selected IO bank. Is that right? If yes, then what is the reason to denote certain pins on the Altera Cyclone II package as dedicated pins for DQ input/outputs?

With best regards, Vladimir S. Mirgorodsky

Reply to
v_mirgorodsky
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=_NextPart_000_0007_01C64A80.E6AEC300 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

The DQS signal is usually associated with a group of data (DQ) pins; so = where ever the DQS singal is you want the associated DQ pins located in = close proximity. Also, some DDR2 I/O standards, like SSTL-18 class II, = are only supported on two sides of the chip.

Reply to
Rob

Hello Rob,

Dedicated DQ pins on Altera Cyclone II package have very strange placement and I am curious about the reason those pins are called DQ. In other words, does DQ pin have any significant difference from the adjacent non-DQ pin in the same bank on Altera EP2C8F256 package?

With best regards, Vladimir S. Mirgorodsky

Rob wrote:

ever the DQS

some DDR2 I/O

Reply to
v_mirgorodsky

What are you trying to do? If you're not using the DQ pins for a memory interface then treat them as standard I/O.

Reply to
Rob

Hello Vladimir,

DQS/DQ/DM-placement is important. The DDR interface requires correct placement of the LEs and routing to the IOB. Quartus does this only for the DQ-pins specified in the datasheet (even it would maybe be possible for other pins as well by the hardware, but the software does not support this). In my design I had mixed up some DM and DQ-pins (I believed that are handled equally when I made the layout, but this is not the case) -> 3 of my 32 DQ pins are not recognized as DQ pins and the design does not compile. (I found a workaround for the prototypes, but require a layout-change for mass-production...)

Regards,

Thomas

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Reply to
Thomas Entner

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