Hello group,
I have an issue with porting my high-speed DDR interface to Altera Cyclone II device. As far as datasheet says, Altera Cyclone II device does not have any dedicated circuitry to support DDR signaling in its Input/Output blocks for DQ pins. The only thing present in hardware is the clock delay circuitry on DQS pins. All other DDR logic is implemented using LUT's and triggers from adjacent Logic Array Blocks. So, it seams that we have only DQS pins location fixed, whenever all other DDR pins may float within the selected IO bank. Is that right? If yes, then what is the reason to denote certain pins on the Altera Cyclone II package as dedicated pins for DQ input/outputs?
With best regards, Vladimir S. Mirgorodsky