hi, i want to write a verilog module for a 32 channel MUX with data width of 8. following is the module i wrote and it compiles successfully.
=============================================================================== `timescale 1ns / 1ps
module mux(data_out, data_in[0:31], sel, en, reset);
parameter data_width = 8; parameter zbus = 8'bz; parameter zerobus = 8'b0;
output[data_width-1:0] data_out; input[data_width-1:0] data_in; input en, reset; input[4:0] sel;
reg[data_width-1:0] data_selection;
assign data_out = (!en) ? ((!reset) ? zerobus : data_selection ): zbus;
always @ (data_in, sel) begin data_selection = data_in[sel]; end endmodule
====================================================================== however im experiancing some difficulties in writing the test bench for it. i've wrote the following but it does not compile.
======================================================================= `timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 22:47:36 05/02/2006 // Design Name: mux // Module Name: mux_tb.v // Project Name: com_link // Target Device: // Tool versions: // Description: // // Verilog Test Fixture created by ISE for module: mux // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////
module mux_tb_v;
// Inputs reg [7:0] data_in[0:31]; reg [4:0] sel; reg en; reg reset;
integer k;
// Outputs wire [7:0] data_out;
// Instantiate the Unit Under Test (UUT) mux uut ( .data_out(data_out), .data_in[0:31](data_in[0:31]), .sel(sel), .en(en), .reset(reset) );
initial begin // Initialize Inputs for(k=0;k