Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Virtex6HXT PCIe doesn't come up to Gen2 on Sandy Bridge systems
I have an 8X PCIe core in a Virtex6HXT (version 2.5, the latest in 13.4). It's configured for Gen2 but it's coming up Gen1. lspci -vvv reports that both the core and the board are Gen2 capable. I've...
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12 years ago
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Difference between Xilinx isim and modelsim
Is it allowed to pass a member of a std_logic_vector to the rising_edge function? When doing this, isim doen's detect all changes, while modelsim does. The code below toggles bits of a 3-bit vector....
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12 years ago
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regarding tft controller
hi, can you please tell me how to add xps_tft controller ip core in xilinx edk for spartan 3e fpga board platform? --------------------------------------- Posted through
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12 years ago
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Active-HDL/Xilinx Core FIFO Gen Sim Problem
Hi there, I'm using Xilinx 10.1(nt) K.31, and Aldec Active-HDL 8.1 (student). I used Aldec's design flow tools to implement a Coregen FIFO, and am using a recent, manufacturer-compiled version of...
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12 years ago
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Relative paths in EDK user repository TCL script
Hi, I'm trying to create EDK repository with my own pcores. In one of this pcores I need to use special program to generate one of its VHDL source files. So during synthesis I need to execute...
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12 years ago
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Post-synthèse simulation
Hello, I want to run a post-synthesis simulation. I don't find where to choose the sources (Netlist post-synthesis) to launch the needed simulation from ISE 13.3. Does someone know how to do it ? I...
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12 years ago
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CFP : The 3rd International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies (HEART 2012), Okinawa, Japan, 30 May - 01 June 2012
************************************************************************ CALL FOR PAPERS The 3rd International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies -- HEART2012 --...
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12 years ago
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Design Notation VHDL or Verilog?
any comments on either VHDL or Verilog?
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12 years ago
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TCP/IP
Hello somebody Know how to link matlab with any device with tcp/ip comunication Iam david.
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12 years ago
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Comunicacion tcp/ip matlab
Hola, desearia conocer la comunicacion tcp/ip cuales son los comandos o algun link donde estas sentencias se hayan probado con algun dispositivo. ojo es en matlab version 7.6 EsTOY HACIENDO UN...
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12 years ago
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OT : No daily abridged emails
Hi all, I have been a long time member of this group receiving 1 abridged email eve= ry day. A month ago I stopped receiving it with no reason. I unsubscribed a= nd subscribed again to the group, and...
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12 years ago
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FPGA not working after programming from EEPROM
Hi, I am using xilinx spartan 3 xc3s4000 FPGA in my design interfaced with two gigabit phyters from National and I have xilinx xcf16p EEPROM on board to program the FPGA. When I program the FPGA using...
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12 years ago
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Open source cable server for Xilinx - for remote running of tools like Chipscope with unsopported target
Hi, II'd like to know if there exists an open source implementation of Xilinx cable server, allowing to run it on a platform for which Xilinx does not provide binaries. Of course it is possible to...
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12 years ago
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slow edge on clk inputs
Are there any simple practical [fpga internal] solutions to aviod internal "ringing" on slow (edged) clock inputs on fpga's, other than resampling and filtering in a different clock domain? (Using...
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12 years ago
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Semi-OT: Good Tcl Book
More and more I find myself needing to write Tcl. My simulator gets far easier to work with if I've got it scripted than going clicking around. Likewise, all of my configuration and control files...
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12 years ago
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