Field-Programmable Gate Arrays

regarding tft controller

hi, can you please tell me how to add xps_tft controller ip core in xilinx edk for spartan 3e fpga board platform? -----...

0 comments posted 14yrs

posted by gnanadeepika423

0 comments posted 14yrs posted by gnanadeepika423

Active-HDL/Xilinx Core FIFO Gen Sim Problem

Hi there, I'm using Xilinx 10.1(nt) K.31, and Aldec Active-HDL 8.1 (student). I used Aldec's design flow tools to imple...

2 comments posted 14yrs

posted by roleohibachi

2 comments posted 14yrs posted by roleohibachi

Relative paths in EDK user repository TCL script

Hi, I'm trying to create EDK repository with my own pcores. In one of this pcores I need to use special program to gene...

3 comments posted 14yrs

posted by lukaskekely

3 comments posted 14yrs posted by lukaskekely

Post-synthèse simulation

Hello, I want to run a post-synthesis simulation. I don't find where to choose the sources (Netlist post-synthesis) to...

5 comments posted 14yrs

posted by molka.benromdhane

5 comments posted 14yrs posted by molka.benromdhane

CFP : The 3rd International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies (HEART 2012), Okinawa, Japan, 30 May - 01 June 2012

************************************************************************ CALL FOR PAPERS The 3rd International Workshop...

0 comments posted 14yrs

posted by k.benkrid

0 comments posted 14yrs posted by k.benkrid

Design Notation VHDL or Verilog?

any comments on either VHDL or Verilog?

35 comments posted 14yrs

posted by henry.val.scott

35 comments posted 14yrs posted by henry.val.scott

TCP/IP

Hello somebody Know how to link matlab with any device with tcp/ip comunication Iam david.

2 comments posted 14yrs

posted by david.samniego

2 comments posted 14yrs posted by david.samniego

Comunicacion tcp/ip matlab

Hola, desearia conocer la comunicacion tcp/ip cuales son los comandos o algun link donde estas sentencias se hayan prob...

0 comments posted 14yrs

posted by david.samniego

0 comments posted 14yrs posted by david.samniego

OT : No daily abridged emails

Hi all, I have been a long time member of this group receiving 1 abridged email eve= ry day. A month ago I stopped rece...

1 comments posted 14yrs

posted by jozamm

1 comments posted 14yrs posted by jozamm

FPGA not working after programming from EEPROM

Hi, I am using xilinx spartan 3 xc3s4000 FPGA in my design interfaced with two gigabit phyters from National and I have...

5 comments posted 14yrs

posted by a1234573

5 comments posted 14yrs posted by a1234573

Open source cable server for Xilinx - for remote running of tools like Chipscope with unsopported target

Hi, II'd like to know if there exists an open source implementation of Xilinx cable server, allowing to run it on a pla...

3 comments posted 14yrs

posted by wzab01

3 comments posted 14yrs posted by wzab01

slow edge on clk inputs

Are there any simple practical [fpga internal] solutions to aviod internal "ringing" on slow (edged) clock inputs on fp...

5 comments posted 14yrs

posted by mleikvol

5 comments posted 14yrs posted by mleikvol

Semi-OT: Good Tcl Book

More and more I find myself needing to write Tcl. My simulator gets far easier to work with if I've got it scripted tha...

4 comments posted 14yrs

posted by rgaddi

4 comments posted 14yrs posted by rgaddi

MicroBlaze MCS Error.

Hi all. I'm T.Koyama. I download ISE 13.4 and make IP Microblze mcs. I could make IP and bitstream,and I make ELF file...

3 comments posted 14yrs

posted by basaro.k

3 comments posted 14yrs posted by basaro.k

clock enable question

I created the following clock enable block: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity...

3 comments posted 14yrs

posted by james.knoll

3 comments posted 14yrs posted by james.knoll