Latest threads in Field-Programmable Gate Arrays

Virtex6HXT PCIe doesn't come up to Gen2 on Sandy Bridge systems

I have an 8X PCIe core in a Virtex6HXT (version 2.5, the latest in 13.4). It's configured for Gen2 but it's coming up G...

0 14yrs

schvantzkoph

0 14yrs schvantzkoph

Difference between Xilinx isim and modelsim

Is it allowed to pass a member of a std_logic_vector to the rising_edge function? When doing this, isim doen's detect a...

6 14yrs

guenter.wolpert

6 14yrs guenter.wolpert

regarding tft controller

hi, can you please tell me how to add xps_tft controller ip core in xilinx edk for spartan 3e fpga board platform? -----...

0 14yrs

gnanadeepika423

0 14yrs gnanadeepika423

Active-HDL/Xilinx Core FIFO Gen Sim Problem

Hi there, I'm using Xilinx 10.1(nt) K.31, and Aldec Active-HDL 8.1 (student). I used Aldec's design flow tools to imple...

2 14yrs

roleohibachi

2 14yrs roleohibachi

Relative paths in EDK user repository TCL script

Hi, I'm trying to create EDK repository with my own pcores. In one of this pcores I need to use special program to gene...

3 14yrs

lukaskekely

3 14yrs lukaskekely

Post-synthèse simulation

Hello, I want to run a post-synthesis simulation. I don't find where to choose the sources (Netlist post-synthesis) to...

5 14yrs

molka.benromdhane

5 14yrs molka.benromdhane

CFP : The 3rd International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies (HEART 2012), Okinawa, Japan, 30 May - 01 June 2012

************************************************************************ CALL FOR PAPERS The 3rd International Workshop...

0 14yrs

k.benkrid

0 14yrs k.benkrid

Design Notation VHDL or Verilog?

any comments on either VHDL or Verilog?

35 14yrs

henry.val.scott

35 14yrs henry.val.scott

TCP/IP

Hello somebody Know how to link matlab with any device with tcp/ip comunication Iam david.

2 14yrs

david.samniego

2 14yrs david.samniego

Comunicacion tcp/ip matlab

Hola, desearia conocer la comunicacion tcp/ip cuales son los comandos o algun link donde estas sentencias se hayan prob...

0 14yrs

david.samniego

0 14yrs david.samniego

OT : No daily abridged emails

Hi all, I have been a long time member of this group receiving 1 abridged email eve= ry day. A month ago I stopped rece...

1 14yrs

jozamm

1 14yrs jozamm

FPGA not working after programming from EEPROM

Hi, I am using xilinx spartan 3 xc3s4000 FPGA in my design interfaced with two gigabit phyters from National and I have...

5 14yrs

a1234573

5 14yrs a1234573

Open source cable server for Xilinx - for remote running of tools like Chipscope with unsopported target

Hi, II'd like to know if there exists an open source implementation of Xilinx cable server, allowing to run it on a pla...

3 14yrs

wzab01

3 14yrs wzab01

slow edge on clk inputs

Are there any simple practical [fpga internal] solutions to aviod internal "ringing" on slow (edged) clock inputs on fp...

5 14yrs

mleikvol

5 14yrs mleikvol

Semi-OT: Good Tcl Book

More and more I find myself needing to write Tcl. My simulator gets far easier to work with if I've got it scripted tha...

4 14yrs

rgaddi

4 14yrs rgaddi

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