Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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kicad or orcad virtex5 symbol
Hi all, I'm designing a board based on a virtex5 (XC5VLX50). I'm surprised, I can't find virtex 5 symbols for using with orcad or kicad. I only found a post explaining how to create symbol in orcad...
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16 years ago
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code coverage in modelsim_se
how to merge multiple missed coverage files to see final uncoverd lines in one file? thanks in advance.
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16 years ago
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Free Background Check
I ran across this site and its pretty neat. You can sign up for free and conduct your own background check. Free Background Check
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16 years ago
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JTAG interconnect testing, prototypes
Hi, I am looking at various alternatives for interconnect testing, especially for prototype boards that have BGAs. I am very interested to know what other people are using for JTAG interconnect...
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16 years ago
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FiberChannel SOF
Would some one know why SOF/EOF of Fiber Channel frame is 4 bytes? Thanks Walters
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16 years ago
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Opteron performance tuning (for Quartus / Linux)?
Thanks in advance for the help! ---------------------------------------- My employer just acquired a SunFire server w 16 dual-core Opterons (model 8220, 2.8 GHz) and 128GB of RAM. Despite the faster...
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16 years ago
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Virtex 13?
I was just eating some spicy food for lunch and I started wondering whether Xilinx would eventually come out with a Virtex 13 family or would they skip it due to superstitious reasons? Thanks. Bob
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16 years ago
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How to do one hot state machine in verilog for Xilinx V5 using XST
I would like to use one hot state machine in verilog. I am using Xilinx V5 FPGA and XST synthesis tool. May i know the verilog syntex to do one hot? Thanks. CP
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16 years ago
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Daisy chaining FPGA with CPLDs
I'm not even sure if this might be a stupid question. I have a Xilinx app note on daisy-chaining FPGA configurations, but can Xilinx CPLDs be placed on the chain as well?
4
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16 years ago
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Problem about ADV7181B debugging
Hi, Everyone. I am debugging an image capture board. In this board, th ADV7181B is used to digitalize one channel analog TV signal and the analo video signal is AC-coupled to ADV7181B input pin AIN6,...
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16 years ago
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Best way to export XPS project to ISE?
I have a design that was built with XPS 8.2.03. I want to lock down everything in the design except one custom OPB peripheral I created. I want other users to be able to modify that peripheral (from...
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16 years ago
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xup-v2p: Only USB 1.1
Hello, I'm working with a new xup rev. 04 board: Whenever I connect the integrated USB Platform cable I only get USB full speed (1.1) although I need the faster USB 2.0 connection. I tried 4 different...
1
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16 years ago
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JPEG-LS hardware implementation
Hi All, We are an enthusiasts who are written hardware JPEG-LS IP core. Visit project site It's working in the simulator and we are sure about it. Although sufficient effort should be applied to...
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16 years ago
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Optimized bitcounting on FPGA
Hi, I am currently working on a circuit which has to perform Hamming distance computation between large bit vectors (>500 bits). I was surprised not to find much information on how to implement this...
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16 years ago
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FFT core
[posted to + Hi All I've had a quote from a 3rd party to develop a floating point FFT core for us (1Mpt). Probably for a Xilinx Virtex5 SXT. Obviously I'd like to get some more quotes, but would like...
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16 years ago
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