Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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FPGA not in boundary scan
Hi I am using Impact and Xilinx Multilinx cable to communicate to my FPGA board. I was able that the connection to the board is established, but somehow I just see a CPLD instead of a Virtex II FPGA...
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16 years ago
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Adding Desing to an Xilins Platform Studio project
Hi, I'm trying to add an existing project which successfully synthesized and simulated with ISE 8.2 and Modelsim to an XPS-project. It's verilog / VHDL Mixed, with the top-module being verilog with...
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16 years ago
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Gnd plane coupling with DDR routing from FPGA <-> DDR?
Hopefully some of you guys who have gone through this can comment... We're doing our first board with a couple of DDRs and have a query with ground plane coupling when routing the signals out of the...
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16 years ago
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SLICEL : 92%,SLICEM 2%
PAR failed because "unable to find location..." Sounds like I'm out of SLICEL . Reports said SLICEL : 92%,SLICEM 2%, other kind of resources less than 60%. Since there are a lot of SLICEMs PAR use...
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16 years ago
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DDR2 controler
Hello, I am currently using the DDR2 controler from XILING (under MIG1.72) for a VIRTEX4. I am encountering a problem of access speed when I write to the memory. Each time I access the memory, my...
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16 years ago
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I/O short circuit protection?
On the Spartan-3 with Vcco at 3.3V in LVTTL mode if I want to protect the outputs from possible miswiring to GND or +3.3V or Output-2- Output. Is there any common practice way to accomplish this? I'm...
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16 years ago
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Behavioral Simulation working but Post-route Simulation is not.
Hi, I have been working on a project and get the coding done and tested using Behavioral Simulation. However, I download it into the FPGA(Spartan 3), it wouldn't work. So I went back and discovered...
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16 years ago
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device utilization
Hi all, I am little confused with naming of different family devices.....In vertex V which i should consider as number of slices... for example: Device utilization summary: ---------------------------...
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16 years ago
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What tools do you use ? Why ?
Hello all, can you please tell us what tools you prefer? Please give some arguments, why you like them. I currently use very intensively Linux shell and GHDL compiler for simulations and XST for...
7
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16 years ago
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area group constraint problem
Hello together, in my vhdl design for ISE 9.2 I want to partition the component instances of the submodules in my toplevel into defined areas of my fpga ic. I have never done this but had seen some...
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16 years ago
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Xilinx IO leakage when not powered
HI I have a Xilinx Spartan3e IO pin connected to a system bus signal. The system bus signal can be active (3.3v/0v) even when the Spartan device is powered off. When the signal is at 3.3, I suspect...
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16 years ago
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What's the difference for VHDL code between simulation and synthesis?
Hi, The following is from Xilinx "Synthesis and Simulation Design Guide". Could you give me an example to show their differences? And explain a little to me? Thank you very much. You may need to...
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16 years ago
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Fedora 8 and ISE 9.2
Hi, I am trying to install ISE 9.2 on a Fedora 8 machine, but have numerous problems. Is there anyone that managed to do this? /michael
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16 years ago
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CPU design uses too many slices
Hi, currently I am designing (as an amateur project) a 32bit Stack oriented CPU with two stack-pointers (Data Stack/Return Stack) and some additional registers, that are partly purely auxiliary,...
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16 years ago
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Xilinx Multilink Connection not working
Hi I have a Xilinx Multilink cable that I would like to use to communicate with a Xilinx VirtexII that is hosted on a PCI Mezzanine board. I connected the PCI Mezzanine board with the cable following...
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16 years ago
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