I suspect he was meaning with a smaller pin count. What you say regarding inductances is perfectly true. However, I think there might be a market for FPGAs/CPLDs which were better optimised for simpler boards. If you have a design with signals running at 200 MHz, you need to be using BGA packages with multiple power and ground balls spread around the package. However, most embedded boards are not running at that sort of speed. If an FPGA package were designed to be limited to external I/O speeds of, say, 50 MHz, then it could be made far simpler for designers. The could use PLCC or TQFP packaging (with fewer pins for the same number of logic elements), or BGAs with convenient power pinning (such as power rings, rather than mixing the power balls with the signals). Internal speeds would not be unduly affected.
And talking about mini-PCBs - another nice idea would be to have appropriate bypass capacitors inside the package for high density components, so that you only need a few bigger caps on the board.