What arch's do you look forward to in 2006?

Whatever we make most profit from working on. (As long as it doesn't have Metrowerks or Green Hills tools). ;)

pete

I like to see some ARM Cortex-M3 processors

The MSP430F2xxx with a hardware multiplier in there.

Regards, Joerg

On 19 Jan 2006 02:33:57 -0800, "rektide" wrote in comp.arch.embedded:

I'd like to have an IBM/Sony/Toshiba Cell processor, the one that's going to be in the playstation 3. At reasonable prices in reasonable quantities.

Not so much hardware, as software: a *free* GCC toolchain for the Infineon TriCore. There's currently (afaik) only 2 toolsets available: HiTec GCC and Tasking. Neither free.

The TriCore could power some neat robotic projects, but > Happy new years! Welcome to 2006. I'm a little late, but thought I

(a) A resurrected Harris RTX2000 with larger addressing space and a "normal" life span.

(b) Non-Harvard AVR processors. (or rather, no Harvard architecture processors at all, period.)

(c) Byte addressing and hardware support for multiple breakpoints in Texas Instruments

(d) Large gate count FPGAs in PLCC packaging (or something else a hobbyist can handle at home)

(e) Open/public bitstream formats for FPGAs, so I can play with my own design tools.

Not embedded hardware, but still in my wish list:

(f) Hewlett-Packard/Agilent manufacturing RPN calculators like in the good old days.

Yes, I know, none of this is likely to happen ...

Roberto Waltman

You are not alone Roberto, I too share some of your dream.

Three vendors [Atmel, Ramtron, SiLabs] are expanding their 1 Cycle C51 family offerings in 2006 - good to see that range expanding. and most ARM variants - tend to have better peripheral bandwidth.

-jg

Yup.

Ditto.

Well actually less and less manufacturers are bothering with DIP / PLCC packages. That will be a serious issue eventually. True enough, if we get some high gate count FPGAs in "hobbyist-grade" packages, it will be up to us to fill the gaps.

Could be useful indeed. Especially in the above situation!

Oh gawd yes...

Maybe tomorrow, maybe someday! :)

D.

Also, large gate-count devices have large IO pin counts (that's just geometry: roughly, pin_count = 4 * sqrt(number_of_cells). It's just the relation of the squares on a chessboard, to its perimeter. Think what a PLCC with 1000 or so leads would look like! At 0.5mm pitch, that's 125mm on a side - it's not a package, but a mini-PCB.

This should be possible, using modern FPGAs ? How about

-jg

I'd like to see this, too. Brooks' comment about the lead-inductance confuses me, though: in the olden days we used to be able to control the slew rate of the IO pad and select low rates to minimize ground bounce. Are slew rates no longer configurable on the IO pads?

Besides, I think a low IO count / high gate count FPGA would be great for hobby use. I typically consider CPLDs for this sort of thing now, but it'd be great to have a few order of magnitude more gates to play with ;)

While I would welcome a public bitstream format, I remember using the vendor tools a dozen years ago - you started a bitstream load with one fingertip on the top of the FPGA, and the other finger on the power switch. When the tools mangled the bitstream and the part latched up, you could remove power before the chip cooked itself. Maybe.

I don't look forward to playing with another alpha-quality open source bitstream tool.

I picked up the 'new' RPN calc (33S) and can't say that it's replaced my trusty 42S for daily use. The v-shaped buttons are weird, the unit is too thick, and the unit generally feels less rugged than the old ones. But the tactile feel is good, the 2-line display seems pleasantly huge for my eyes, and the functions I care about are available.

Kelly

1. The sheer number of IO's (you may design to avoid simultaneous switching, but the chip maker can't depend on that).
2. Apart from the IO, core switching, which knocks back on the power leads. Even an inexpensive part like a small Xilinx Spartan may now need

The chip makers' prime markets want speed: they don't care about BGA packages, since they outsource assembly to well-equipped factories anyway. Let's be honest here, hobbyists have no commercial clout.

Whats' the 1 cycle mean? fully pipelined, 1 instruction execution per clock?

Shouldn't the source for any GCC port be available because of GPL ? AFAIU the actual compiler is available for free, but that you get extra propriety libraries optomised for the TriCore when you buy the HiTec tools. Maybe a port of something like avr-libc combined with GCC toolset would be viable ?

Regards Anton Erasmus

There are applications where the logic inside is large but the I/O count is relatively small (usually pipelined algorithms video/audio processing) that does not need to access memory or need large I/O.

Forgetting hobbyists there many applications built that are in small runs (less than 1k in product LIFETIME) where BGA production is not a viable option.

All that happens is less and less deiversity and creativity will happen in the the long term fewer design companies are actually making anything new unless they can million+ volumes. The designers in all teh companies up the cain become dependent on each other, so that as soon as one folds it has major economical impact on the rest.

Wondering for example what is going to happen to Intel when PC manufacturers really start closing down, due to not enough people buying new computers every 6 months.

These days, 1 cycle means at least one opcode can execute in one clock. Back in the mists of time, N8051's needed 12/24/48 clocks per opcode, then some clock doubled, then newer cores arrived, with /2, or /1 clocks, and some have wider memory fetches, which also expands the bandwidth. Other companies with 1 cycle C51's are ST (uPSD-USB) and STC

-jg

Actually, I think i saw an RPN calculator by HP at the local friendly Walmart the other day. I think it 's called the 33S.

I thought HP was going to quit making calculators.