vhdl code

Feb 25, 2009 2 Replies
J

I have to generate digital PWM from UP-1 board.ALTERA UP-1 board has internal clock where the value is 25 MHz. These clock needs to be divided first in order to can create PWM with 40 kHz frequency and 0.75 duty cycle.Can someone send me a VHDL CODE for a clock divider. Please show by example, I'm new to logic design.


Thanks,



jebei


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L

Wrong group. Try comp.lang.vhdl

Also try

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T

Or comp.please_do_my_work_for_me

http://www.wescottdesign.com
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