FSK modulator/demodulator

What stability do you require? +/- a few percent , or +/- a few ppm?

If the latter, a DSP based modulator and demodulator clocked from a TXCO could work.

Regards, Allan

probably about +/- 1000ppm. It depends on how fare the 2 frequency are apart.

Seems as a expensive solution

Regards, Rasmus

A stability of 0.1% is not doable with pure analog. Did you have a look at a DDS such as the AD9833 ?

Rene

They need to be at least the baudrate apart. Better a bit more.

It is to expencive

I thought so. So they need to be a least about 300kHz apart (min.

It doesn't need to be all analog

few ppm?

frequency are

They need to be at least the baudrate apart. Better a bit more.

If there is a good balance of 0s and 1s in the bitstream you are transmitting, then it's fairly easy to use a PLL to make the (analog) modulator frequency stability as good as that of a reference crystal.

The PLL will need a fairly low loop bandwidth to avoid causing excessive baseline wander.

The PLL will also need a fairly low comparison frequency to avoid the problem that occurs when the phase modulation on the output (due to the FSK) scaled by the feedback divider exceeds +/- 2 pi radians, which is the linear range of the phase detector.

You might need to use a scrambler to ensure a good balance of 0 and 1.

Regards, Allan

A DDS would make a great modulator. Maybe too expensive?

Another option is to use a PLD to divide down some convenient crystal frequency. You would switch back and forth between two divisors. The output would be a square wave which you might have to filter.

For example, 10 MHz divided by 5 is 2000 kHz and 10 MHz divided by 6 is

Or, if you are willing to go to a 100 MHz crystal. Then you can divide by either 100 or 125. Let's say that a logic "1" is 1 MHz (100 MHz/100) and a logic "0" is 800 kHz (100 MHz/125). Then you can generate a 1 by sending 5 full cycles of the 1 MHz clock, and a logic 0 by sending 4 full cycles of the 800 kHz clock. You can play around with different clock frequencies and divisors until you find a setup you like. But the good thing about this is that in either case, 1 or 0, the baud period is exactly 5 uS, giving exactly 200,000 baud per second.

You can also use a DDS-like continuous phase technique inside your PLD. That is, you have a phase accumulator, and a phase increment. Every clock cycle you add the increment to the accumulator, and store the sum back into the accumulator. The MSB of the accumulator is your output. You toggle back and forth between two different phase increments to get your two different frequencies. The application notes and datasheets for AD's DDS's explain this in detail. If you go this route, there is no need to go faster than 10 MHz.

For a demodulator, some kind of PLL would seem to be the only reasonable solution, since you already seem to have rejected a DSP. But I am not an expert in this stuff.

HTH

--Mac