MC9S12GC pwm problem

Hi to all. I'm new to this processor so I may be doing something dumb here , but I cant get the PWM output to go over 50Khz. I am working in Codewarrior v5.5.1272. I have tried setting up the pwm using the "processor Bean" functions and doing the settings manually with the same results.The bean shows that I should be getting 5Mhz output , but I'm getting 50 KHz. I seem to be 100 times off in frequency.I'm using clock B as the source , with prescalar set to 0 (bus clock).If I set the prescalar to 4 I get a output of 12.5Khz instead of 1.25Mhz.The internal frequency is supposed to be 25Mhz. Is there any way I can accurately check this. I have tried toggeling a pin in an infinite loop. This shows the pin toggeling at about 250ns , with other interrupts etc running.The processor internal bus can't be running 100 times to slow!! My 1ms timer is also spot on. Any ideas. Cheers Rob

Reply to
seegoon
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Are you setting up the system clock and waiting for PLL lock?

Reply to
Go

I have put in a delay(3s) before the PWM is set up. This seems to make no difference. The pll must have stabilised by then.My 1ms timer is running spot on so I assume the internal bus is running at the correct speed. Rob

Reply to
seegoon

Assuming that your system and bus clocks are okay, are you certain you're selecting Clock B as your PWM clock and NOT Clock SB? If your clock selection is okay, then you've really got to take a hard look at the system clock. If you're using BDM, you can scope the ECLK pin for your bus rate while your app is running.

If the system clock has not been config'd, you're not going to get a SYSCLK at 25MHz.

Frank

Reply to
Go

Hi there. I am definately running Clock B.First thing I checked. I am using the P&E usb multilink module. Where do I check the bus rate? Cheers Rob

Reply to
seegoon

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How are you determining that the pwm clock is 50 kHz? Surely all you can see is the repetition rate of the pwm signal. That rate will be divided from the pwm clock by the number of pwm steps (minus 1). So if you have 101 duty cycles - 0% to 100% in 1% steps then repetition period will have been set to

100 clock ticks (or multiple thereof). 50 kHz for a pwm doesn't seem unreasonable to me. If you want 5 MHz output from a 25 MHz clcok then the pwm will only have six different duty cycles (0/5, 1/5, 2/5, 3/5, 4/5, 5/5).

Peter

Reply to
Peter Dickerson

Hi there. I'm measuring the period of the output. I see what you are saying though. If I want to go higher in frequency I will have to reduce the number of step I can use.I have reduced the Channel period from 256 to 125. I can now get to about 100Khz. I assume I'll only have half the number of steps though. Sort of makes sence , but I will have to delve deeper into the datasheet to get a better understanding of how it all works. Cheers Rob

Reply to
seegoon

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