Frequency Doubler - VHDL/Verilog

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You can't make a symmetric-duty-cycle frequency doubler in digital logic = unless you have a precisely controlled delay element.

Many thanks for your input !

Regards,

Michel

Assuming the clock is always running and at least in the ballpark of

Can I fixup the duty cycle with a cap, inverter, and big feedback/bias resistor?

If I'm willing to go off-chip and back in, will that work for the

Hal, I like your line or thought, and I have been thinking along the same lines, without good results. Maybe this community can come up with a simple solution: Use a few external components to adjust the duty cycle, and perhaps also the alternate period problem. For simplicity: accept a relatively low frequency (

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HI, You didn't say anything about the frequency, so maybe for lower = frequencies one way is to cascade 2 of these 2f circuits to get a 4f = frequency and then using a simple flipflop to divide it by two, get a = perfect 50% duty cycle 2f signal.

Many thanks for your input !

Regards,

Michel

Arash, That won't work. Try drawing a timing diagram to see why! cheers, Syms.

Many thanks for your input !

Regards,

Michel

Doubling again and then dividing does not solve the problem. It just gets you back where you were. :-( Peter Alfke

On a sunny day (Wed, 12 Nov 2003 13:55:30 -0800) it happened Peter Alfke wrote in :

Well, the analog way was to make a coil with a center tap and 2 diodes. The double phase rectified wave you get is 2f ( like 120 Hz hum from 60 Hz supply). This works fine for analog (amplitude modulated) signals too, I have used it a 4.43 MHz to double color subcarrier. You will have to go off FPGA, drive a small ferrite transformer, slice it with a transistor, and back into FPGA. In these days many people are paranoid about discrete components perhaps. Not to mention a coil or transformer. But it is really simple. Of cause any non-linear component (MOSFET / FET / Transistor) can be used to double frequency, just bias it in the non linear region, and put a circuit tuned to

tuned to

If you think about this, you are asking for 'clairvoyant logic'

- it has to know where to put the extra edges, in order to give symmetric output. You CAN double Freq, to get an OP positive edge for each IP edge, but the OP falling edge has no IP info to relate to, so is device delay determined.

So, you will need some analog interpolation scheme - that can be :

- Accept fixed freq operation, and design appx delays as nominal 50%

- RC integrator & comparitor, to give quadrature signals which can then be doubled to close to 50%.

- narrow band tuned circuit, ringing at target 2f

- Full PLL approach

-jg