What is the problem with this ?

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There is expensive software that will take VHDL and create a schematic, apparently for people who aren't sure what they have designed. The output I've seen looks like something one of my cats would cough up.

It's tragic that there is not an industry-standard ascii format to express schematics, like the LT Spice thing.

John

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Then they're flip-flops. ;-)

No, only if the groundrules specify edge-triggered FFs. All IBM (bipolar) mainframes used latch pairs or PHs ("latches" and "triggers") as their register elements, and most is strictly synchronous. Even the CMOS versions use latches, though they're better hidden. ;-)

I guess maybe! They throw so many it's impossible to ferret through them to find the ones that will bite, and there are many. Decent software would have the warning messages switchable by class, type, and instance to allow the dangerous ones shine through the fog.

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I've used such things[*] but never found one that was useful for anything more than very small bits of logic. Synplicity had one a decade ago that would show either logical or technology views. Both were very useful to learn what language constructs produced what sorts of logic, but totally useless for anything more.

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You should swat your cats. One of ours has a "sensitive stomach" and spits up its food regularly but has never made a mess like that.

Until you can see what synthesis produces these tools are important in learning how to herd the cats.

VHDL is pretty standard. ;-)

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Those are called "fatal errors."

John

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No, "fatal errors" are those that will prevent synthesis. Many "warnings" will tell you that you are producing trash, but producing it nonetheless. Ignoring warnings is dumb, but hardly criminal given that one important needle may be lurking among a large pile of useless hay. I always pick through all warning messages at least once before a design review (it should be a requirement of said design review).

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Way back in the late 1960's i remember seeing the equivalent circuits for ttl master slave flip flops and edge triggered flip flops. The circuits were very different and the described action was very different as well. In particular if you had a longish clock input on the master slave it would not change the output until the clock went back to the rest state; whereas the edge triggered would always change within some x number of nanoseconds regardless of the level on the clock input. (Assuming setup and hold conditions were met.)