What is the problem with this ?

Well, the logic would be interesting at least, even if utterly impractical. So just use it for smaller numbers, NBD. Represent larger numbers with different forms, like digits or powers -- that's how bigger numbers always end up represented anyway (in order of scale: digits, matissa with exponent, exponents of exponents, raising operator). That's just implementation, and as long as you've cooked up a Turing-complete computer, it doesn't really matter in the end.

I think the biggest impracticality that people think is, well how the hell do you represent 1000? With a thousand wires? That's absurd of course, and besides, it demands that there be a zero (7 = ...00000001111111), and that isn't necessary. (There is the necessity of null as the absence of one, however. In that sense it is still binary.) Indeed, a number can be represented on just one wire, and electronic rules require that to be something like voltage or current or time. (Frequency, phase, impedance (complex!) and more properties can be sent down wires, but I can't imagine how complex an impedance-signaled computer would be to construct!) Time would be easy because, digitally, it could be ticked off in discrete quantities with a clock (a bus could be self-clocked, so only data and ground wires are needed, which would look something like a serial line, but self clocked). Notice that a counter is nothing more than an unary-to-binary conveter. ORing together the edges (XORing?) of two data streams and clocking a counter forms an adder, or using an up/down counter, data streams to count-up and count-down forms a subtractor. By clocking in one number and adding it to itself (the addition could be done in binary just for expediency...) with each clock of a second stream, a rate multiplier is formed. If two data streams start simultaneously, it is clear to see which number is larger: the lesser string stops first. If they don't start simultaneously, you can count the number of cycles before the next start and adjust for it, which just goes back to the subtractor, which is fundamentally what a comparison is, after all. Representations of real numbers can be produced with arbitrary timings, though moving to the analog domain, uncertainty becomes the limit to accuracy.

Alternately, as HardySpicer observed, voltage could be used. The physical phenomenon of voltage can even be seen as unary, which is kind of fun. Noise of course puts a limit on accuracy. Interfacing to regular digital circuitry is similar, using an ADC/DAC instead of a counter. There is one advantage to analog: exponents are easy to compute, thanks to exponential function blocks being all around us: the silicon junction.

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No. It does not make any sense. How long does the compare take? Answer the question (well, now two questions).

Can you say very many doubts?

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Is there even a proper definition for that?

That is nice, just be sure you initialize your twisted ring counter properly.

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What distorted timeline did that come from? DEC self destructed from the internal conflict of VAX versus Alpha.

As a Kid i invented my multiplier:

The multiplicand was accumulated multiplier times. Numbers got larger and i discovered more effective ways.

This isn't quite what you're talking about, but an interesting real-life use of this sort of thing is a flash A/D converter (not to be confused with the unrelated and much more recent FLASH memory), which uses a large number of comparators (to convert N bits takes 2^N comparators). The positive comparator inputs all go to the signal input, and the negative inputs go to successive taps on a resistor string with a DC voltage across it. As the input voltage increases, more and more comparators turn on as the voltages goes over that at its tape in the resistor string.

This gives a number of 1 outputs proportional to the input voltage. These can then go into a logic block called a "thermometer encoder" which converts the highest '1' bit into its corresponding binary value.

Bijective? I hope that means both injective and surjective (one to one and onto). Not that this guess is any clearer for many people here.

The good circuits (e.g. Spehro's or the CD4017) self-correct if they get into a disallowed sequence.

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That might be the view of somebody internally, but IMHO as an external DEC user/customer, the problem began when they started trying to compete with IBM in the mini-mainframe market. DEC did great with small lab machines up through the 1980's and early 90's, even after their marketing division completely began ignoring the market in the late 80's in their push to sell only mainframe-class machines.

Don't get me wrong, VMS's clustering technology was and still is way cool, and has many uses outside the mainframe-class world.

Tim.

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Aren't all latches transparent?

Xilinx' rules/technoloy/software hates latches. Other's have nothing but. When in Rome, do as the groundrules writers do.

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They were on the skids well before Alpha. In fact, Alpha was their=20 only possible salvation. One corner, as told by the insiders, was=20 when the suits demanded they be called "d*i*g*i*t*a*l", rather than=20 "DEC".

As always, you have your head firmly up your ass.

--=20 Keith

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No. Some are edge-triggered, such as 74HC74.

...Jim Thompson

I went through the multiplier => adder tree phase as a kid.

That's when I discovered that counters weren't the only use for sequential logic. ;-)

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That's a D-Type master-slave flip-flop, no matter what the mustard bible says.

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Of course, that's how "edge-triggered" is accomplished.

Brings back a question I've broached before. Any VHDL or VHDL-like program that generates schematics?

...Jim Thompson

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The point is that it is not a latch.

I don' know of any freebies, and the ones I've used aren't any good for documentation (further than ports). They draw bug ugly schematics. One alternative is to use schematic entry for top-level and data flow, with VHDL for state machines. I find it easier to just bite the bullet and go all VHDL for chips and schematics for boards.

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What I'd like would be a program... feed it a clocked truth table and have it spit out a gate-level schematic.

...Jim Thompson