1. Home
  2. Electronics Design
  3. What are these capacitors for?
  4. Page 4

What are these capacitors for?

Tim Williams wrote on 10/27/2017 1:16 PM:

Yes, the reactive impedance goes to zero limited only by the ESR.

Not sure what your point is. This impedance minimum doesn't go away in the circuit. It may be shifted somewhat, but it's still there.

Did you have a point with any of this? You state a lot of general stuff and don't tie it into the discussion.

The "best case" impedance is not so important unless you have specific frequencies you wish to damp. But it is always difficult to damp specific frequencies with specific component configurations. Most of the characteristics which are used here are parasitic and so may vary if the components are substituted or a small change to the circuit is required for other reasons. Much better to go for a uniform adequate impedance across the frequency range unless there are special requirements.

Yes, no surprises there.

--

Rick C 

Viewed the eclipse at Wintercrest Farms, 
on the centerline of totality since 1998
Reply to
rickman
Loading thread data ...

If I understand correctly the fix was to modify the FPGA design to reduce the large fluctuations in power changes at the resonant frequency? Was this a particularly large Virtex4?

--

Rick C 

Viewed the eclipse at Wintercrest Farms, 
on the centerline of totality since 1998
Reply to
rickman

only difference is time domain vs frequency domain.

--
This email has not been checked by half-arsed antivirus software
Reply to
Jasen Betts

On Friday, October 27, 2017 at 3:19:38 PM UTC-7, rickman wrote: ...

his

...

Yes - that was the main fix. I also added a bunch of decoupling and tuned the supply voltage that gave incremental improvements. Once we had it work ing i didn't go back and remove those other changes so I'll never know if t he code change would have been enough by itself.

I don't remember which particular Virtex 4 device it was but it was one of the largest in the family and it was fairly full - we needed 5 FPGAs togeth er to house all the logic we needed. Also I think what made it particularl y bad was that a large proportion of the logic was in the same pipeline wit h the 4 out of 5 clock activity rhythm. I suspect if there was more random logic in the device it wouldn't have been so much of an issue.

kevin

Reply to
kevin93

It's just interesting that it even happened. How did Xilinx figure it out? Was this something they were aware *could* happen? One of the reasons the decoupling recommendations are so over the top is because of the wide variety of consumer designs. Likewise, it would have been inevitable that sooner or later a customer would have a design that stimulated this resonance.

--

Rick C 

Viewed the eclipse at Wintercrest Farms, 
on the centerline of totality since 1998
Reply to
rickman

We normally bring a few FPGA i/o pins out to test points or SMA connector footprints. One could then program a pin to ground or to the bank Vcc and snoop the noise there. Some chips would probably let you access Vcc_core that way too. Since there are many Vcc_core pins, one of them could be (carefully) sacrificed as a snoop, too.

--

John Larkin   Highland Technology, Inc   trk 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin

On Friday, October 27, 2017 at 5:40:59 PM UTC-7, John Larkin wrote: ..

...

We didn't try that, thats a good idea.

Even then it would probably only allow the voltage going into the interposer to be snooped and not the on-die voltage. Maybe Xilinx has some way of bringing that out.

This was about 10 years ago on an obsolete version of the product so things have changed a lot by now.

kevin

Reply to
kevin93

On Friday, October 27, 2017 at 5:30:18 PM UTC-7, rickman wrote: ...

... They didn't tell how they knew just gave us various bits of information and suggestions on how to fix the problem - it took us a couple of PCB spins to solve on a board that had must have had more than $10,000 of parts on it.

The $25,000 FPGAs I'm using now are even pricier and they are not top of the range! Better make sure I connect that power the correct way round :-)

kevin

Reply to
kevin93

I'm not sure why you think that. The I/O pin is not really connected to the power rails in the chip package. They have some parasitic capacitance and inductance, but other than that LRC filter you should see the voltage from the chip power distribution.

--

Rick C 

Viewed the eclipse at Wintercrest Farms, 
on the centerline of totality since 1998
Reply to
rickman

You can reuse FPGAs, if they're expensive enough to warrant the pain and clearly yours are. That doesn't mean you don't have to check and recheck your footprints, though. ;-)

Reply to
krw

On Friday, October 27, 2017 at 11:25:57 PM UTC-7, rickman wrote: ...

...

Sorry - I was referring to the core voltage that was causing the problems.

You are right about the I/O pin being able to sense the I/O bank voltage on die but I don't see how there is a way to sense the core supply.

kevin

Reply to
kevin93

Actually in analog circuitry it can cause oscillation. In digital it more like pollutes the digital signal(s).

Reply to
jurb6006

Yes, you are right. I was forgetting the I/O pins are powered from separate circuits in most FPGAs.

--

Rick C 

Viewed the eclipse at Wintercrest Farms, 
on the centerline of totality since 1998
Reply to
rickman

I fixed one mobo with bad caps where what I had in stock was too large to f it. I found that C had dropped to a tiny fration of nominal values before t he thing failed, so figured it would probably live with long leads on the C s. It was fine. In hindsight I probably would have been better going down a step on C value.

NT

Reply to
tabbypurr

Found an 8 pin socket earlier this year that had let go entirely, turn the thing upside down and the C fell out. I don't like sockets much.

NT

Reply to
tabbypurr

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.