What are these capacitors for?

Feedback thru the rails to the input stages can easily happen in simple discrete amps because the PSRR of say a CE transistor or CC tube stage + load resistor can't be any better than what's implied by the Thevenin equivalent of the device dynamic impedance in parallel with the load resistor voltage divided into the input impedance of the following stage. Which is usually garbage.

It can also happen in single supply op amp circuits when there's insufficient bypassing on the "virtual" ground which often is both defined by a voltage divider from the positive supply and "real" circuit ground and connected to one of the input pins via a feedback resistor and gets injected that way.

For this discussion I define "low frequency instability" to be say 1MHz or something within the gain-bandwidth product of audio op amps. HF is HF like the radio definition, 10s or 100s of MHz. Can an audio op-amp oscillate at 10s of MHz? You bet, but it can't be a round-the-whole-loop phenomena how could it? There's a compensation cap inside, the open loop input-to-output transfer function has a dominant pole at very low frequency, as a whole it has no gain way up there. The V->I stage can't possibly smash current in and out of the compensation cap fast enough to make it happen.

In this block diagram of an op amp where is the feedback loop thru the PS getting in to make it unstable at HF? It definitely can't be anywhere prior to the 30pF compensation cap:

They probably just used whatever they had a lot of/was cheap. For audio op amps the precise value of the caps likely isn't super-critical; anything between 10nF and 1uF might be fine depending on the specific part.

They sometimes put small ceramics in the 10s or 100s of pF in parallel with the feedback resistors, too, to well-define a high-frequency -3dB point for the stage.

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bitrex
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You're just too funny Phyllis.

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krw

His expertise ends at 20 KHz.

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John Larkin

Yes, like recommending hundreds of caps on one FPGA. But lately they seem to be getting more reasonable, like a dozen caps per FPGA. Maybe the on-chip caps are helping there.

When a paper is co-authored by a guy from AVX or Kemet, be a little skeptical.

I saw one board being assembled, part of an Anritsu dram tester, that had 3000 bypass caps.

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John Larkin

----------------------

** JL's autistic, pig ignorance has no limit.

.... Phil

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Phil Allison

STOP IT! You're making my sides hurt, Phyllis!

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krw

On Wednesday, October 25, 2017 at 7:32:40 PM UTC-7, John Larkin wrote: ...

... Occasionally they are appropriate.

I had one design that would sometimes have errors.

Adding extra caps helped, tuning the supply voltage up a few millivolts hel ped, beefing up the supply (putting another 30A module in parallel) helped but they didn't cure the problem.

Eventually with Xilinx's help we determined that the package was resonating at about 30-35MHz. The FPGA was processing data for a high-speed 43Gbps o ptical link. The processing algorithm had a 168 MHz clock divided into 5 ti me slots but only 4 were actively used, there was not much being done in th e fifth.

Ensuring that the FPGA kept busy during that fifth time slot cured the prob lem.

The accepted explanation was that resonance on the core power line was the culprit, excited by the difference in power consumption during that last ti me slot. Tens of amps change within a few nanoseconds can cause lots of vol tage disturbances.

kevin

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kevin93

Actually, at your age, more like 8 or 10 KHz.

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John Larkin

You are talking about a resonance on a trace inside the FPGA chip, right? That's scary.

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rickman

snipped-for-privacy@tubes.com wrote on 10/25/2017 1:23 AM:

They are placed near the source of noise or on power inputs that need to be filtered.

Actually you are showing your ignorance of RF design. Even high quality audio tube circuits have paid attention to layout by keeping distance between inputs and outputs to prevent oscillation and lowering of frequency response.

Modern solid state ICs can provide a huge improvement in density which puts all the "wiring" closer together increasing the parasitic effects. The circuits often have a much higher frequency response as well. This leads to problems with feedback at very high frequencies or in the case of digital circuits, crosstalk between signals. Sure, make your digital designs from discrete transistors and they will be as large as a barn and you won't need to care about layout so much. But they will run 100 times slower as well.

They can only sell parts as long as the parts are made. Even passives change (getting better) over a couple of decades.

Sockets and other connectors are a major source of failure in electronic design. Chips and passives are made well enough to last many decades. Connectors are exposed to the air and other contaminants and so will oxidize and corrode with time. I consulted with a manufacturer of a smoking cessation device once. They had intermittent failures because of the socket the chip was in. They started soldering the chips to the board.

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rickman

35MHz is well within the bandwidth that the PCB designer needs to account for. It's the 100MHz+ range that has to be handled on chip.

Power planes can be a hazard as much as a boon. They are extremely low impedance capacitors, with only modest loss, so they resonate with the ESL of anything you tack onto them. You need to use at least as many bypass caps as the sqrt(ESL / Cplane) (lower is better) and 1 / (2*pi*sqrt(ESL * Cplane)) (very high or very low is better) the chip needs to run at.

A 5nF power plane resonates with 0.5nH (say 6 x 0.1uF 0603s with a pair of vias to the side, each) at 0.31 ohm and 100MHz. A 10A transient load at

100MHz would develop 3V of ripple!

Tim

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Tim Williams

So do you know?

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rickman

Tim Williams wrote on 10/27/2017 2:57 AM:

Not sure of the purpose of your post. You didn't really address the question.

With nearly every MLCC cap having a null above 100 MHz, I don't see how the power supply trace on a PCB could resonate at 35 MHz. Well, actually, I don't know what they mean by "core power line" as any adequate PCB for FPGAs would have power planes, not traces. So none of this is making sense for me.

BTW, your resonance issue is moderated by the ESR of the discrete caps. I don't see where you took that into consideration. Just as the impedance nulls are moderated, the peaks are moderated. Then you can use another size of MLCCs with different ESL so the peaks of each is covered by the lower impedance of the other. Some would say to use many sizes, but I don't think that is needed.

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rickman

On Thursday, October 26, 2017 at 10:38:22 PM UTC-7, rickman wrote: ..

...

Yes - within the BGA package itself. That's not on the silicon but within the PCB and bond wires to the die. This was a Virtex4 FPGA without in-package decoupling. Supposedly the package resonance was typically in the 30-50MHz for this type of packaging.

Since it is within the package it can only be influenced slightly by what is done on the PCB itself.

The modern FPGAs such as Virtex Ultrascale that I am now using have in-package decoupling and only require a small handful of capacitors on the PCB.

kevin

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kevin93

Some capacitors are truly on-chip, tens to hundreds of nanofarads.

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John Larkin

I have added SMA connectors to a few board layouts, so I could TDR the unstuffed board power planes with and without the bypass caps.

As close as doesn't matter, a pour over a ground plane is a perfect capacitor, and its capacitance value goes up as you solder in more bypasses anywhere on the plane.

Maybe high power RF would care about the truth of that statement, but the usual logic and analog stuff doesn't seem to object.

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John Larkin

If it truly is the fault of the chip's interposer, no matter what's done on the PCB, then that's pretty damning, but I would suspect the majority of cases where supply ripple problems appear, are ultimately the fault of the PCB. I was illuminating that case.

Null?

Do you mean the ESL + C series resonance valley?

A component has a given impedance curve, in a given fixture. It's somewhat meaningless in circuit. As soon as you connect traces to the pads, and vias to the traces, you're modifying the component, and the curve changes.

Connect parts in parallel, and it changes further still. Often in undesired directions!

Well, it's a "line" to the extent that it has line-like properties.

Connections to the plane have an approximate length dimension. I don't mean the vias: I mean the lateral current spreading, within the plane itself, around a via.

If the plane is rectangular or necked, that's another length dimension.

Often, a plane is zero-dimensional, which is the approximation I used earlier, and which Larkin used below.

A plane is actually three dimensional, but those dimensions only become relevant for very low impedances (fractional ohms) and very high frequencies (where waveguide modes appear). Though those are probably also at high enough frequencies that the FR-4 will be quite lossy, and the modes will all just kind of smoosh together, making their consideration even still less practical. :)

This is convenient for us, as circuits are zero-dimensional. A symbolic circuit has no physical size, it is an abstract graph -- there's no speed of light in SPICE!

Yes, the impedance peaks are limited by the losses of the caps, the load itself, and whatever loss the FR-4 has at that frequency (probably not much). This gives Q factors in the 5-20 range, which is a considerable disadvantage compared to a well damped PDN, that might have a higher best-case impedance but lower worst-case impedance too.

Stacking caps is a false economy; Dave Jones did a tutorial on it semi-recently, but committed the fallacy of stacking impedance curves and drawing a line through them.

Impedances just don't do that.

Example:

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You should find this a reasonable enough model -- it's a tantalum "bulk" cap, say on the output of a regulator, connected via some trace length (a few inches?) to a triple stack of caps (say, 0805, 0603 and 0402) of decreasing values. V1 is used to measure the impedance looking into this network (one can also move V1 left of L4 to measure PSRR instead).

These values would be typical of a single sided layout, with maybe 0.5mm spacing between caps, and VCC/GND traces stringing them together, up to a VCC/GND pin pair.

For an inner plane layout, L5 and L6 go away (and L4 may shrink or disappear as well), and L1-L3 represent the component lengths, plus a pair of vias placed beside each one. (Note that the components do not need to be placed close together, nor close to the device pin, because the plane is ~ideal. Note also that sharing caps on the same pair of vias isn't helpful.) Then, add an ideal cap from V to GND to represent the plane capacitance (which might be a few nF in typical cases, but YMMV).

Here's the sausage:

formatting link
Note that the stack of caps has created three notches (not nulls, the impedance is always finite and nonzero), and two rather tall peaks (both over an ohm each).

Tim

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Tim Williams

Yeah, a few nH here and there definitely affects beefy FPGAs and CPUs, and tons of vias are needed for RF, especially power RF.

The only way to deal with the plane's ponderously low impedance, is to try your best to beat it at its own game: load it with as many caps (and vias -- use 4 vias per cap!) as you care, so that the parallel equivalent of all those ESLs is comparable to the plane's.

At this point, you'll also have a low enough impedance that the individual cap ESRs provide damping. You might even supplement with a "bulk" cap that's aluminum polymer: the low ESR can otherwise be a bad idea, but in an environment with impedance this low, their ESR looks like a good juicy tantalum.

Exactly this design approach is clearly visible in most anything that needs it -- server/supercomputer CPUs from the 90s up, and consumer CPUs from Slot Pentiums (it was all on the card, of course) to present day. The CPU socket is always filled in, around, or underneath, with oodles of ceramics.

Incidentally, note that motherboard manufacturers don't see it necessary to stack different values or sizes for this job!

Tim

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Tim Williams

On Friday, October 27, 2017 at 9:36:41 AM UTC-7, John Larkin wrote: ..

ackage decoupling and only require a small handful of capacitors on the PCB .

...

I assume it is the on-chip capacitors resonating with the interposer/bond w ire inductance that was causing the basic problem. I was surprised how low the resonance frequency was. We couldn't measure it (apart from failures i n operation of the FPGA). Once we found a fix we didn't research it any mor e. We didn't have a problem with a follow on design using Virtex5.

kevin

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kevin93

No, there is a lot of nonsense, backed up by silly Spice sims, that justify putting three caps of different values at each bypass site. In real life, the system is low-impedance and low Q. I use 1 uF everywhere, which is not many places. If a chip could change its current by amps in microseconds or milliseconds, like a big CPU or something, some bulk capacitance might be needed to help out the regulator. Some 47 uF ceramics or polymer aluminums maybe, for super low ESR.

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