TI also sells a DSP-ish chip that has a PWM output with a final delay- line stage that gives you finer clock resolution.
I know Joerg wants an analog input. _I_ want to tweak Joerg a bit!
-- Tim Wescott Wescott Design Services http://www.wescottdesign.com
A 555 or other teeny thing wrapped with integrating feedback, to hold the average at precisely what you want? It kinda violates your "one chip" desire, but at least it can be done with a minimum of small parts.
-- Tim Wescott Wescott Design Services http://www.wescottdesign.com
It's only a dual comparator and a transistor! The first comparator is set up as a Schmitt trigger with thresholds at +Vs and -Vs; its output drives a resistor to the base, capacitor from collector to base, emitter to V-. That makes a triangle wave. The second comparator takes signal in on one input, and triangle wave on the other, and you're done.
It's possible but when assuming a master clock of 20MHz going in and I'd want, say, a 1k granularity that would result in an effective PWM of only 20kHz. Unless I am understanding something wrong in the datasheet.
What I'd essentially need is a class D audio modulator but without the DC cut-off. Unfortunately that's as rare as it is on audio CODECs where only a few such as the AD1939 can go down to DC without onerous offset issues or huge drift.
-- Regards, Joerg http://www.analogconsultants.com/
The current source would be fixed, not variable "over a wide range." That's trivial.
555 comparator drift might be a problem, but there might be precision versions without it.The 555 is cheap and small enough that it's almost worth using just for the internal logic...
Cheers, James Arthur
If that's the usual silicon delay line deal I don't want it. Took my lumps there, or rather a client did and when they called me in all I could do is rip it all out and design an analog solution. The digital delay section had the noise performance of a pressure-assist loo during the flush :-)
Which IC do you use for generating the PWM? Creating a number would be as easy as dropping in an ADC. Most sigma-delta chiops I've seen use a fairly low clock frequency and you don't get the granularity needed at a sufficnetly hig PWM frequency. I could drop the upper frequency to
500kHz if hard-pressed but not a lot lower.-- Regards, Joerg http://www.analogconsultants.com/
But their timers won't run faster than MLCK and that seriously limits the granularity if the PWM has to pipe out at a MHz. I'd need almost a Giggeehoitz. Not that it can't be done but that's a really fat CPU.
-- Regards, Joerg http://www.analogconsultants.com/
Digital is ok but 1000:1 granularity at a MHz or at least half a MHz would require a fat processor with really good timer resources.
Not too complex but all the phase noise measurements I did on digital delay lines so far almost made me throw up.
My wife's already trying that since a few decades :-)
-- Regards, Joerg http://www.analogconsultants.com/
I am going to do something like that (but probably not with a 555) if nothing single-chip comes up. That's the reason for this thread, to see if there isn't anything out there. I mean, every class-D amp must have a super-linear PWM generator. It's just that most have the power stages built in (would be ok, can be left idle) and have lousy or no DC performance (would not be ok).
-- Regards, Joerg http://www.analogconsultants.com/
Okay, that narrows the field--too fast for a 555!
It's going to be hard to get good linearity from any consumer part, and it's hard to imagine who'd need it other than class-D audio.
Cheers, James Arthur
yes, a fixed frequency PWM 0..100% generator, use that myself. :)
Jamie
Sure, I know how to do it analog. But it's not quite as simple as it looks. Offsets, drift, regulators for super-stable rails et cetera. I thought there's got to be a solution-in-a-can because of all the class D amps these days. But the problem seems to be DC because audio doesn't need that. So maybe there isn't a suitable IC.
-- Regards, Joerg http://www.analogconsultants.com/
Then the comparator in the IC must do the job and be good, and they normally aren't.
That's the trade-off.
Yes, or go with an analog solution like whit3rd mentioned. But then you'll have to make sure the offsets and all that are handled which makes it all not as trivial and low in real estate as it looks.
-- Regards, Joerg http://www.analogconsultants.com/
That's the reason for starting this thread: Class D. They use PWM in the hundreds of MHZ in order to get away with small magnetics yet it's quite linear.
The DC stability is the issue, most audio ICs barely have any to write home about.
-- Regards, Joerg http://www.analogconsultants.com/
with DS is hard to talk about pwm frequency, it has noise shaping so the switching noise gets pushed to higher frequencies. i.e if you are exactly midrange the "pwm frequency" would be 10MHz
with a brick wall reconstructions filter you would normally gain 3dB every time you double the sampling frequency, with a second order deltasigma you gain ~15dB, first order ~9dB
if you can live with the higher switching frequency I think deltasigma would do that
-Lasse
I can't live with a switching frequency that gets much past a MHz in certain areas. It will cause large losses in the attached power electronics. I'd like the PWM to be at least somewhat constant in frequency. It isn't critical though, if it varies even 50% that would be ok. But not a lot more.
-- Regards, Joerg http://www.analogconsultants.com/
Are you sure they aren't digital inside, with 2nd- or 3rd-order sigma- deltas to make up the bit count?
-- Tim Wescott Wescott Design Services http://www.wescottdesign.com
You originally said 50-1000kHz. At 50, I'd use an ST ARM-core micro running at 48 or 50MHz.
If _all_ you're doing is generating PWM at 500kHz you could probably still do that. You'd get 1% or 2% steps in your PWM (some of those chips limit the PWM clock to 1/2 the core clock). To get delta-sigma you'd need to use DMA, though, which is getting beyond simple for most folks.
On the bright side, at a 500kHz PWM frequency and a 15kHz "I care" bandwidth, a simple 1st-order delta-sigma modulator would buy you roughly five bits of precision -- at that point, your error drivers are probably asymmetries in the power circuitry, rather than the actual behavior of the PWM.
-- Tim Wescott Wescott Design Services http://www.wescottdesign.com
No DC performance can't be fixed -- but lousy DC performance could be fixed with feedback, assuming there's an appropriate loop frequency to make it easy, yet have enough authority at low frequencies to clean up the crap.
(And no microprocessor -- see, I can propose analog solutions to analog problems).
-- Tim Wescott Wescott Design Services http://www.wescottdesign.com
Yes, that's the range I need this to be able to operate in.
It has to have 0.1% granularity or better.
Not really. My most recent project contains a uC-generated PWM at 12-bit granularity. Of course, that can only run at 2kHz. We could still double the master clock for a 4kHz PWM at same granularity but the power consumption penalty would be too much for this application.
-- Regards, Joerg http://www.analogconsultants.com/
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