Voltage to PWM chip (similar to class D)?

That's a problem, my signal path goes all the way to DC and the loop would be a pain.

And I did a project with a uC in there last month. Plus one the month before. But ... other than prescribing how I want the code to flow and what the individual chunks of it should do the programming was done by others.

I like things analog if possible. Like my new mountain bike (which by now looks like it came back from a war zone), in contrast to cars those do not contain any uC. On higher-end road bikes that is already starting to change where some have electronic shifting. Couldn't believe it.

Only if you needed it "right away", if you could average 100 cycles, then you could do it with 10MHz.

George H.

Can the pulse width be dithered or does each pulse width have to adjust to within 0.1% of the needed value? I think a digital solution could do this if you just need the average pulse width to match.

This is starting to sound like a job for FPGAman! Where's my cape? Durn, at the cleaners after that messy SERDES job.

Well I don't really know what I'm suggesting, but can you patch up the DC response of an audio IC? (maybe someone already did that?) George H.

Dither is a problem. If it's dithering between 2-3 consecutive pulses, maybe, but it would be a serious compromise.

This does not mean I am ruling anything out at this point, it's just that I'd first like to see if there is a class-D chip that can be pressed into service. Thise have very clean PWM, just not down to DC because offset voltages and stuff aren't important for audio.

I bet an FPGA with some minor analog sprinkles around it could do this job nicely. But that would be like using a Porsche to go to the grocery store.

That's sort of a variation on delta-sigma: PWM, but dither it one clock to interpolate the output. Full delta-sigma has too many transitions.

With some CODECs you can. However, so far all the ones I looked at except for the AD1939 have sloppy offset specs. But this was for another project, it can't do PWM.

That would have the phase noise performance of a steam locomotive :-)

We have one product where we used 16 channels of 1 GHz SERDES to make the equivalent of 16 PWMs, each with 1 ns resolution. We can make pulses of any delay and width by streaming clever patterns into the SERDES fifos.

And what is wrong with that? Porche makes a mom-mobile! FPGAs come in lean, mean sizes for any budget. If you are short on board space they even come in some pretty teeny-tiny packages if you don't mind very fine pitch BGA type things. Otherwise they just come in small packages.

Actually a digital approach would need either the comparator that you seem to not like or an ADC which might be a better match. If you need up to a 1 MHz pulse rate I assume you would need a 1 MHz ADC sample rate which is not too hard, but it would start to use a few mA. It's been a while since I've looked at ADCs at that rate but I know they are not hard to find, especially with only 10 or 12 bits.

The rest is easy... 1 GHz clock might be a bit tricky in one of the very low power FPGAs, but maybe. The dual latches used for DDR work might just enable this on a pretty low power device. It would be an interesting design task. Either way one of the conventional FPGAs could handle this easily I'm sure and the smaller ones don't suck so much power. I could poke around a bit if you are interested.

For the ritzy crowd with beaucoup disposable income, yes.

It is like shooting a fly with a 50mm canon. The fly will be killed dead for sure, as John Wayne would say, but it's overkill. We have no people who can program FPGA. It ain't in the budget (yet).

The required rate of change is only up to about 15kHz and transferring the analog control signal to digital at 100ksps or so is a piece of cake. Can be done with a very tiny ADC.

Maybe not just yet because I want to find out whether we can just plop in a class-D chip. We don't have a budget for an extra FPGA design for this phase. But that could change when this becomes a product and I'll keep you in mind (assuming you can legally do freelance work, as in not bound by an employer).

I'm not clear on your answer. To make sure you understand what I am suggesting... You can use a slower counter clock if you dither the pulse width. In reality you would need to use some feedback similar to a sigma-delta circuit. The pulse width would only vary from ideal by a fraction of a count at any one time and the error could be accumulated and used to add a delta on the next pulse width. Another plus is that the feedback loop can be internal to the digital circuit since the error source is the low order bits that are being truncated.

I think John Larkin has picked up on this judging from his post. The question is whether the small instantaneous deviations will make a difference. Similar to sigma-delta the "noise" would be at a high frequency.

What this means is that my filter after the power stage would have to roll off at lower frequencies, to combat the resulting noise. That lead to two not so nice effects: Larger magnetics in a product where small size is very important. Also more ringing upon rapid control signal changes which becomes harder to mitigate the lower the ringing frequency is.

Have you looked at the price of a Honda lately? There are *no* cheap cars.

You can make any analogy you wish, but mostly people just don't "get" FPGAs. You have no people with FPGA experience, so I expect you won't be learning much more about them in the future. They really aren't so hard.

The requirements seem to be a bit vague. So the sample rate would only need to be 100 ksps? So why is the pulse rate up to 1 MHz? Can the pulse widths be dithered across 10 pulses? That can lower the clock rate by 10x.

Yeah, I get that. Simpler is better and if you understand it well, that makes it simpler.

No employer other than myself. :) Happy to help if you need it.

I know a guy, if you're ever interested. We swap Visio block diagrams to define the function, and then he codes it.

Some of the so-called CPLDs are actually small FPGAs with internal flash, cost roughly $1.50 in low volumes. It's liberating to have all that logic available.

There are. A friend bought a new Kia Soul for around $13k. It is a remarkably practical car. My SUV was just shy of $18k in 1997, new, and one can probably find a similar one for maybe $3-5k more these days.

It doesn't have to be a fancy car.

First I'll learn uC some more. I grok their HW innards but am a bit rocky when programming. FPGA would be next in line since there is less opportunity to use one in my field. I do get peeks into the world of FPGA sometimes because I always work for several clients simultaneously. Some are bigger companies who have FPGA coders.

In pretty much any a PWM-driven power stage the PWM frequency must be several times higher than the highest spectral components in your control signal. You could theoretically get away with it at the Nyquist limit but the filter requirements would be onerous. Remember that the filter is always in the power path so everything gets big, heavy and expensive. Keeping the PWM frequency well north of 10x makes this job almost infinitely easier.

Good. It's similar on another project where I did everything with some hardware and a PC last year. But if all goes well we will develop the real product this fall and then a uC specialist will become involved whom we could not use for cost reasons so far. Luckily he is local, about 20 minutes via mountain bike or car (40min with a regular bicycle).

Yes, they sure are tempting. In the past FPGA have always turned me off because they were either power guzzlers or went unobtainium all the time. The only series that I really liked was from Intel with true CMOS behavior, meaning power went to almost zero at low clock. But then Intel dropped the ball again. I had almost used them in a design. That could have resulted in a serious black eye. But what I understood from what Rick said in the past this has become better where some series will be around for longer.

Many of my designs require 20 or 30 years of production life. That rules out a lot of stuff that others take for granted.