I have a requirement to terminate an AC coupled 100MHz clock and producean LCVCMOS (3.3V) 50MHz clock with low jitter (the amount of jitter isn'tspecified).The input is specified as an "AC coupled signal of 1mW into 50 ohms".I don't have any experience with low jitter clock distribution so amunsure how to approach this. I currently have the clock terminated thenac coupled and biased into a LT1715 (150MHz comparator) feeding a single gated type flip flop but am not confident this is the best approach.Once you've all stopped rolling around laughing, I'd appreciate anypointers to a better approach.Thanks in advance,Nial.

That sounds reasonable. Expects low 10s of picoseconds RMS jitter,maybe below 10 if everything is perfect. Maybe worse if the signal isnoisy.Adding a tuned circuit on the front end can help jitter performance alot, by dumping ground loops, RF, any non-10-MHz stuff. If you designit to add a bit of voltage gain, even better.A faster comparator wouldn't hurt. LVDS line receivers makegreat:cheap fast comparators.John

Termination of AC coupled 100MHz clok to generate low jitter 50MHz clock?

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Jim Thompson 16 years ago

My favorite trick is to make a low frequency "oscillator" by using a shift register (looped on itself) driven by a crystal oscillator, then "injection lock" by resetting the shift register appropriately by comparing lead-lag between signal and shift register state (digital phase detector). ...Jim Thompson

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Jim Thompson 16 years ago

As in...

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...Jim Thompson

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Jim Thompson 16 years ago

And another way...

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in actual use decoding Manchester. Delay blocks are those (now ancient) lumped line delay blocks with TTL-in/TTL-out. ...Jim Thompson

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Termination of AC coupled 100MHz clok to generate low jitter 50MHz clock?

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