I have a requirement to terminate an AC coupled 100MHz clock and produce an LCVCMOS (3.3V) 50MHz clock with low jitter (the amount of jitter isn't specified).
The input is specified as an "AC coupled signal of 1mW into 50 ohms".
I don't have any experience with low jitter clock distribution so am unsure how to approach this. I currently have the clock terminated then ac coupled and biased into a LT1715 (150MHz comparator) feeding a single gate d type flip flop but am not confident this is the best approach.
Once you've all stopped rolling around laughing, I'd appreciate any pointers to a better approach.
Thanks in advance,
Nial.