Termination of AC coupled 100MHz clok to generate low jitter 50MHz clock?

That sounds reasonable. Expects low 10s of picoseconds RMS jitter, maybe below 10 if everything is perfect. Maybe worse if the signal is noisy.

Adding a tuned circuit on the front end can help jitter performance a lot, by dumping ground loops, RF, any non-10-MHz stuff. If you design it to add a bit of voltage gain, even better.

A faster comparator wouldn't hurt. LVDS line receivers make great:cheap fast comparators.

John

gate

The LT1715 won't go faster than 150MHz

as is shown on page 5 of the data sheet (above). A faster comparator might be a good idea.

The Analog Devices AD96685 might be worth looking at, if you can live with ECL outputs.

Their ADCMP567 seems to be quite a lot faster.

but I've not used that device.

John Larkin's point about a tuned circuit in the front end is a good one. I once used a half-wavelength of delay line between the inverting and non-inverting inputs of a comparator to get a little more voltage drive, but three feet of even minature coax could be a bit too bulky for comfort.

-- Bill Sloman, Nijmegen

Bill,

Is this a problem if the input clock is 100MHz?

As usual my request wasn't fully spec'd. I'f prefer to power whatever I'm using just 3.3V, I can provide 5V if I _have_ to.

Space is fairly tight :-)

Thanks,

Nial.

Note that if you're going into an impedance higher than 50 ohms that you can get voltage gain from a resonant circuit. But if you design a resonant circuit you either need some production guy to tune it or you need to do some careful analysis to make sure that it works over manufacturing variation and temperature. You'll definitely have a tradeoff on the Q of the circuit -- higher Q means better noise performance, but worse sensitivity to manufacturing gain.

My inner Diogenes tells me that 'low jitter' with no specification means one of two things: they'll never check, so you can do whatever you want, or no matter what you do they'll come back and complain that it jitters too much.

Press for a jitter spec on your output clock, and one for the input clock, too. Best case you'll just be able to do the comparator thing and call it good. Worst case you'll have to make some fancy PLL circuit to clean up the jitter while tracking the input phase and frequency. It all depends on what you need and what you're starting with.

You can buy 2% surface-mount Rs and Cs these days, so something with a Q of three or so wouldn't be twitchey, and would jam a decent amount of swing into a comparator or LVDS receiver. Even at unity gain, a tuned circuit could help the jitter situation a lot.

John

SN65LVDS2DBVR if you want CMOS output, FIN1101K8X if you'd like LVDS.

Both are 3.3 volt; 58 and 85 cents respectively, faster than the LTC part which is $3.50 or so.

John

Don't you just love those Fairchild LVDS parts?

You should... I was a major player in that design team in 2001 ;-) ...Jim Thompson

Agreed. You may not have to think about it much, but you should still think about it.

Or use the voodoo method, build an oscillator and do injection locking. That's almost guaranteed to produce some jaw dropping in the design review :-)

Makes lock detection fun too.

Injection locking can do some amazing things, but it's a bit like Jan's neural nets--they may work, but it's harder to know *why* they work, so one may reasonably doubt that they'll *always* work.

(Yes, I know there's math that lets you set bounds on injection locking behaviour--unlike neural nets--but good luck getting any of your beer-check buddies to go through it.)

Cheers

Phil Hobbs

Sure. Low jitter design isn't always obvious. Like here, too much Q might make things worse.

John

The curve in the data sheet is for a typical device, not worst case, and it shows you needing 5mV swing at the inpot to get a logic swing -

The data sheet doesn't give upper and lower limits on maximim toggle frequency, but it does give worst case propagation delay ranges from

I'd give myself a little more headroom.

-- Bill Sloman, Nijmegen

Thanks again for the feedback Bill.

More details of the design....

Hmm. The 1mW into 50ohm input I'm told produces about 0.6V (not what I calculated but a real world measurement from the client).

The maximum temp this will operate a is 70 Deg, with a 3.3V supply directly driving a clock buffer with max Cin of 6pF.

The performance characteristics on page 5 (typical) would suggest that I'm no-where near even the 150MHz limit, even degrading this to 66% means I'm still OK.

No?

Nial.

I had such frustration with clients tossing around dBm that I had my son write this little executable...

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

Nice... good way to demonstrate how reference impedances matter. My experience is that many times people are effectively measuring voltages but the displayed result on, e.g., a spectrum analyzer come out in dBm (with an assumed 50ohm reference) which causes no end of confusion. "Why does this amplifier show 25dB gain when it's spec'd at 15dB?" "Because you'r measuring voltage gain and the data sheet is showing power gain..."

---Joel

Used that once to sync a local small uc to the main ref clock of a real sensitive lock-in sync detector and IF board. Run the ref clock track near the uc crystal and voilà.

At the time I was not aware of the term or concept "injection locking", but for personal use I created a PIF12Fxx base serial output frequency logger. Besides running on its own usual setup crystal I wanted to try and see if this minimalist design could be made to work on my 10MHz reference as well. The simplest thing I could thing of was feeding it 10MHz directly to the crystal oscillator input via a few KOhm plus a cap. It was fun to see it move the required tens of Hz when the reference was connected. No switches required. It runs free when standalone and locked when the BNC is plugged in. Cool..

Joop