Ta-da!

Your simulation doesn't include your power input source, presumably a rectifier, based on your label. You also don't show us what the input waveform is (half wave or full wave?) or what the impedance from the input to common is (does it have a DC return?). All of these affect the performance of the circuit and need to be included in the simulation.

It would also help if you identified how you got the results, specifically, which of the many test points shown on the schematic were used for each plot. You know these things but we can only guess.

Full-wave rectified, straight off AC line. +VRECT to -VDC

You should be able to find all the nodes on the schematic? ...Jim Thompson

You didn't show the Vrect waveform. What pulls it down? A bridge rectifier without some pulldown can't keep sloshing charge into/out of the current limiting capacitor.

Replace Vrect with a floating AC supply and a bridge rectifier, and it won't work.

Is the PFC supply on all the time? If so, what is this circuit needed for? It certainly can't be used to start up the PFC, if it needs the PFC for pulldown.

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

Have you built this? Does it actually work?

Yep. I think the Chinese are fudging on me. They show me waveforms with a worst case trough no higher than about 10V off of -VDC. I've asked a New Zealander (in HK, they sort of speak English :-) to run a storage scope view from t=0. I will likely just halve the cap and pick off from a phase... I'm already on the "hot side" any way. ...Jim Thompson

It will be bread-boarded today (Tuesday HK time). ...Jim Thompson

You call me a fraud! Clearly you didn't think this through. Looks like I saved your cookies again. I really should stop doing that.

What's weird is that I pointed out this problem last week, and you're just now catching on to it.

It's rare for the unloaded output of a bridge rectifier to look anything like abs(sin(w*t)).

I was spending my time refining the control for the TRIAC.

The Chinese assured me, and sent a scope photo. The bridge load capacitance is only 100nF... and there's a whole lot of s*it hanging on there that's "defined" to me only as a block.

But, indeed, your nudging raised my concerns, which is why I've requested a look-see by an English-speaking buddy.

Which nudging, in normal _discussion_ is great. But your intent seems only to be an asshole. ...Jim Thompson

==============look here =======================

==============look here =======================

Look at the conversation highlighted above. I pointed out the pulldown problem without personal comment. You replied by calling me a fraud.

OK. My apologies. How about we limit ourselves to strictly electronics from now on? ...Jim Thompson

I for one would like to see this. Of all the possible things I can learn from you two, new ways to insult people is pretty low on the usefulness index.

They aren't even new. They're strictly from the sixth grade, except for replacing "momma" with "wife".

Cheers

Phil Hobbs

of

it

And "hip boots" with "hats" :-) ...Jim Thompson

Agreed, they are well marked on the schematic but not on the simulation results. It would help if the graphs were labeled something like I2 (which matched a current sense point on the schematic).

presumably a

of

it

Nah, not from one of the main perps.

Cheers

Phil Hobbs

Of course I do.

There you go, flailing away, being rude and crude, trying to use slime to cover up that you still can't calculate the inverter interstage capacitance... in spite of the fact that I practically handed you the answer on a platter. ...Jim Thompson

You've lost me there. Did you carefully read the axis labels? Pick a simulation waveform and tell me what you can't connect to a schematic point? ...Jim Thompson