SPICE capacitance question

I've been hashing a little with LTspice lately with making a model or sort of for an SCR.

I've succeeded in making a sub circuit connectable in a block using the primitive functions of spice, current sources, voltages sources etc.. but would like to get a better understanding of the model code itself.

It seems that finding the resources needed for the actual event variables that you need to access in your model code and label variables for C, R, L on inputs and outputs etc are hard to locate..

I do programming in various languages so I have a good idea on how this should all work. I have looked at various models already and have gotten many of my questions answered how ever, It would be nice if there was a plain document on the step by step of the primitive variables that are involved and the names of them you need to know in the model code.

Set sizes , cycle count and things of that sort, so that one can quickly put together a working step circuit.. if you get my drift.

The help file, as good as it is, offers you all the math functions and the like but it seems to come in short when it wants you to understand the under layer of what is to be taken place.

For example, I saw in one example the use of ro, lo, co, ri, ci, li to indicate the basic elements R,L,C in the input or output which makes perfect sense how ever, If that is to be primitive variables of spice, I can't find that documented? Or, what I saw isn't what it is.

Years ago in college I didn't use anything like spice, we did it all on paper and slide rules. Then I got my first TI si calculator and that was a big jump for me :)

Jamie

How about pumping in a sine wave current source and amplifying the node voltage into a synchronous detector and lowpass filter? Or maybe just FFT it.

I like to build my own test equipment in Spice.

John

Do an AC analysis while injecting an AC current into the relevant node. The AC voltage at that node will give you the impedance to ground, the impedance to ground will give you an idea of the capacitance.

I have special macros that give CAPvalue and resistance terms, nicely displayed in Probe. Email for details. ...Jim Thompson

"John Larkin" wrote in message news: snipped-for-privacy@4ax.com...

AC analysis is the obvious solution, but you have to set the DC operating point. Each. And. Every. Time. Remember, I said it's a variable capacitance. Sure, you can set a parameter sweep with the bias, but then you get, say, a hundred curves with >2 points per curve and no curve connecting the curves.

Tim

This sounds useful, unfortunately it would have to be implemented in a scripting language (DelphiScript, JS, etc.) working with Altium's API, if it even provides handles to automate this sort of thing in the simulation editor.

Tim

-- Deep Friar: a very philosophical monk. Website:

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

Why not design a c-meter and run it in time-domain mode? Just probe its output like any other signal.

John

"John Larkin" wrote in message news: snipped-for-privacy@4ax.com...

Supposing I run bias from a staircase source (creating the transient equivalent of the AC + parameter sweep setup), I have to wait for ALL signals to stabilize, both bias AND the c-meter reading. This will take more than a few cycles of whatever the c-meter is doing, and a hundred points will take several minutes to simulate.

Then if I want to incrementally tweak the model I'm testing, I have to wait several minutes again.

Plus the time of designing and building the setup in the first place, which is probably a few hours, depending on how involved the c-meter is made to be. It doesn't have to be fancy since it could be e.g. current sources, switches, charge pumping, that sort of thing, but those all cost simulation time.

Tim

Semiconductor junction capacitances are currently characterized base on curve fiting of static data, and the characteritics are applied dynamically. Are you suggesting that this does not reflect real situations?

As in real life, you'd have to couple the 'tester' to the node in question, to minimize loading effects or interference in function. The issue isn't avoided, just because it's a simulation.

Complex impedance measurements can be made, conventionally, to extract reactive components.

It's a little ironic, as the solution to any spice node's characteristics should be solvable mathematically - it is a construct, after all. As we adopt models and tools that are more complex - that we don't completely understand - we require more complex test features to 'simplify' the process of understanding.

I wonder if, in the end, we know more, or less?

Constructing the spice equivalent of test equipment is an activity that is being tried from a number of directions in the LTspice yahoo group. This has included curve tracers and impedance/network analysers.

RL

Well, life sucks I suppose.

John

That's all fine and dandy, but like I said to John, if I implement it conventionally, I have to wait for it to stabilize. I'd love to do it in real time, because heck, I can generate that fast enough to sweep a CRT scope, let alone generate some X-Y points on the DSO in under a second. But doing it in sim is a lot more painstaking. I was hoping someone might have an elegant solution which takes advantage of the environment.

Tim

Do a .AC analysis, with the excitation named (reference designator) "VAC". Then...

CAPINT=IMAG(-I(VAC))*IMAG(-I(VAC))-REAL(-I(VAC))*REAL(-I(VAC)) CAPRES=REAL(-I(VAC))/CAPINT CAPVAL=CAPINT/IMAG(-I(VAC))/(2*pi*FREQUENCY)

If you want capacitance versus bias, parameterize the bias, run the .AC, then use Performance Analysis to plot capacitance versus bias.

(This is in PSpice, but I'm sure a comparable method exists in LTspice.) ...Jim Thompson

If only Tim would read postings to the bottom of the page, he might get somewhere, intead of stewing.

There are all sorts of ways to reduce simulation time. Establishing initial operating conditions is only one of them, though in my line of work it would avoid useful hints about relevant disasters-in-waiting.

RL